coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-02-19	soc/intel/skylake: Disable s0ix if not enabled in devicetree	Duncan Laurie
2017-02-14	soc/intel/skylake: Perform CPU MP Init before FSP-S Init	Subrata Banik
2017-02-14	Revert: soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1	Duncan Laurie
2017-01-20	soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1	Barnali Sarkar
2017-01-11	skylake: Do not pass VBT to FSP if display init not required	Duncan Laurie
2016-12-01	romstage_handoff: add helper to determine resume status	Aaron Durbin
2016-11-30	soc/intel/skylake: Use SendVrMbxCmd1 for FSP 2.0	Rizwan Qureshi
2016-11-30	soc/intel/skylake: Disable Legacy PME for Root ports	Naresh G Solanki
2016-11-28	soc/intel/skylake: Add USB Port Over Current (OC) Pin programming	Subrata Banik
2016-11-21	fsp2_0: implement stage cache for silicon init	Brandon Breitenstein
2016-11-11	soc/intel/skylake: move i2c voltage config to own variable	Aaron Durbin
2016-09-19	soc/intel/skylake: Add FSP 2.0 support in ramstage	Naresh G Solanki
2016-08-31	skylake: Add initial FSP2.0 support	Rizwan Qureshi