| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-09-17 | intel/skylake: Create "RtcLock" Silicon UPD from coreboot | Barnali Sarkar |
| 2015-09-10 | skylake: Enable DPTF based on devicetree setting | Duncan Laurie |
| 2015-09-08 | skylake: Clean up chip.h | Duncan Laurie |
| 2015-08-19 | skylake: Update Memory and Silicon Init params | Rizwan Qureshi |
| 2015-08-14 | skylake: remove ec_smi_gpio and alt_gp_smi_en | Aaron Durbin |
| 2015-08-14 | skylake: provide GPE0 routing devicetree configuration | Aaron Durbin |
| 2015-08-14 | skylake: remove IedSize from chip.h | Aaron Durbin |
| 2015-08-13 | skylake: Add Deep Sx configuration for wake pins | Duncan Laurie |
| 2015-07-21 | skylake: Show SPI controller if enabled in devicetree.cb | Duncan Laurie |
| 2015-07-16 | soc/intel: Add Skylake SOC support | Lee Leahy |
| 2015-07-16 | soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC | Lee Leahy |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |