| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-10-27 | intel/skylake: IRQ programming through UPD | Subrata Banik |
| 2015-10-27 | intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update | Rizwan Qureshi |
| 2015-09-17 | intel/skylake: Create "RtcLock" Silicon UPD from coreboot | Barnali Sarkar |
| 2015-09-10 | fsp1_1: provide binding to UEFI version | Aaron Durbin |
| 2015-09-08 | skylake: Apply USB2 and USB3 port enable/disable settings | Duncan Laurie |
| 2015-08-27 | skylake: only generate ACPI cpu entries once | Aaron Durbin |
| 2015-08-19 | skylake: Update Memory and Silicon Init params | Rizwan Qureshi |
| 2015-07-29 | skylake: remove the redundant fspNotify in chip final. | robbie zhang |
| 2015-07-16 | soc/intel: Add Skylake SOC support | Lee Leahy |
| 2015-07-16 | soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC | Lee Leahy |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |