Age | Commit message (Expand) | Author |
2016-10-16 | soc/intel/skylake: Enable HECI BAR for ME communication | Subrata Banik |
2016-09-02 | Fix newlines at the end of files | Martin Roth |
2016-08-30 | soc/intel/skylake: Include Kabylake specific IGD Device IDs | Barnali Sarkar |
2016-08-18 | soc/intel/skylake: Correct Cache as ram size | Rizwan Qureshi |
2016-08-18 | soc/intel/skylake: Move bootblock specific code from skylake/romstage | Naresh G Solanki |
2016-08-18 | skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init | Rizwan Qureshi |
2016-07-31 | Remove extra newlines from the end of all coreboot files. | Martin Roth |
2016-07-28 | intel/fsp1_1: Add C entry support to locate FSP Temp RAM Init | Subrata Banik |
2016-07-28 | soc/intel/skylake: Add C entry bootblock support | Subrata Banik |
2016-07-28 | soc/intel/skylake: Do cache as ram and prepare for C entry | Subrata Banik |
2016-04-14 | soc/intel: Update license headers | Martin Roth |
2016-02-04 | intel/skylake: unconditionally set SPI controller BAR | Aaron Durbin |
2016-01-12 | intel/skylake: Remove check for Microcode loaded by ME | Martin Roth |
2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
2015-10-15 | cpu/mtrr.h: Fix macro names for MTRR registers | Alexandru Gagniuc |
2015-10-11 | skylake: Leave SPI controller enabled | Lee Leahy |
2015-10-11 | skylake: SPI code cleanup | Lee Leahy |
2015-09-09 | x86: bootblock: remove linking and program flow from build system | Aaron Durbin |
2015-08-13 | skylake: fix garbled patch from upstream | Aaron Durbin |
2015-07-29 | Skylake: Fix microcode reload in bootblock cpu init | Rizwan Qureshi |
2015-07-16 | soc/intel: Add Skylake SOC support | Lee Leahy |
2015-07-16 | soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC | Lee Leahy |