| Age | Commit message (Expand) | Author |
|---|
| 2017-11-15 | soc/intel/skylake: Make use of common CSE code for skylake | Subrata Banik |
| 2017-10-05 | soc/intel/skylake: Add support in SKL for PMC common code | Shaunak Saha |
| 2017-10-03 | soc/intel/skylake: Enable common LPC IP | Ravi Sarawadi |
| 2017-09-22 | soc/intel/skylake: add Kabylake Celeron base SKU | Gaggery Tsai |
| 2017-08-16 | soc/intel/skylake: Add proper support to enable UART2 in 16550 mode | Subrata Banik |
| 2017-08-10 | soc/intel/common/uart: Refactor uart_common_init | Furquan Shaikh |
| 2017-07-11 | soc/intel/skylake: Fix PMC address range setup for PCH-H | Nico Huber |
| 2017-07-11 | soc/intel/skylake: Set generic I/O decode ranges early | Nico Huber |
| 2017-07-01 | soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignment | Barnali Sarkar |
| 2017-06-23 | soc/intel/skylake: Use CPU MP Init Common code | Barnali Sarkar |
| 2017-06-09 | soc/intel/skylake: Use CPU common library code | Barnali Sarkar |
| 2017-06-09 | soc/intel/skylake: Move update microcode from cbfs to mp_ops callbacks | Barnali Sarkar |
| 2017-06-06 | soc/intel/skylake: Use PCI IDs from device/pci_ids.h | Subrata Banik |
| 2017-06-05 | soc/intel/skylake: Add config for cpu base clock frequency | Aamir Bohra |
| 2017-06-05 | soc/intel/common/block: add bios caching to fast spi module | Aaron Durbin |
| 2017-05-18 | intel/common/block/i2c: Add common block for I2C and use the same in SoCs | Rizwan Qureshi |
| 2017-05-09 | soc/intel/skylake: Use intel/common/block/smbus code | Aamir Bohra |
| 2017-05-02 | soc/intel/skylake: Clean up code by using common FAST_SPI module | Barnali Sarkar |
| 2017-04-28 | soc/intel/skylake: Use ITSS common code | Bora Guvendik |
| 2017-04-25 | soc/intel: Unify `timestamp.inc` | Paul Menzel |
| 2017-04-25 | lib: provide clearer devicetree semantics | Aaron Durbin |
| 2017-04-24 | soc/intel/skylake: Add ID's for Kabylake-R | Naresh G Solanki |
| 2017-04-11 | soc/intel/skylake: Use intel/common/uart driver | Aamir Bohra |
| 2017-04-11 | soc/intel/skylake: Use LPSS common library | Aamir Bohra |
| 2017-04-10 | soc/intel/skylake: Use RTC common code | Subrata Banik |
| 2017-04-10 | soc/intel/skylake: Use common PCR module | Subrata Banik |
| 2017-04-06 | soc/intel/skylake: Add support for GSPI controller | Furquan Shaikh |
| 2017-03-28 | soc/intel/skylake: Clean up code by using common System Agent module | Subrata Banik |
| 2017-03-28 | soc/pci_devs.h: Use consistent naming in soc/pci_devs.h | Subrata Banik |
| 2017-03-28 | soc/intel/common/block: Add cache as ram init and teardown code | Subrata Banik |
| 2017-03-24 | soc/intel/skylake: Use C entry code for MTRR programming | Subrata Banik |
| 2017-03-17 | soc/intel/skylake: Fix remaining issues detected by checkpatch | Lee Leahy |
| 2017-03-17 | soc/intel/skylake: Wrap lines at 80 columns | Lee Leahy |
| 2017-03-17 | soc/intel/skylake: Add int to unsigned | Lee Leahy |
| 2017-03-06 | soc/intel/skylake: Clean up CPU code | Subrata Banik |
| 2017-02-16 | soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO... | Sooi, Li Cheng |
| 2016-12-07 | PCI ops: MMCONF_SUPPORT_DEFAULT is required | Kyösti Mälkki |
| 2016-11-30 | soc/skylake: Move IO decode range out from pch_lpc_init | Teo Boon Tiong |
| 2016-11-28 | soc/intel/skylake: Initialize UART based on CONFIG_UART_DEBUG | Teo Boon Tiong |
| 2016-11-11 | soc/intel/common/lpss_i2c: simplify API and use common config structure | Aaron Durbin |
| 2016-11-07 | soc/intel/skylake: Add device id for PCH-Y | Naresh G Solanki |
| 2016-10-27 | skylake: Prepare GPE for use in bootblock | Duncan Laurie |
| 2016-10-16 | soc/intel/skylake: Enable HECI BAR for ME communication | Subrata Banik |
| 2016-09-02 | Fix newlines at the end of files | Martin Roth |
| 2016-08-30 | soc/intel/skylake: Include Kabylake specific IGD Device IDs | Barnali Sarkar |
| 2016-08-18 | soc/intel/skylake: Correct Cache as ram size | Rizwan Qureshi |
| 2016-08-18 | soc/intel/skylake: Move bootblock specific code from skylake/romstage | Naresh G Solanki |
| 2016-08-18 | skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init | Rizwan Qureshi |
| 2016-07-31 | Remove extra newlines from the end of all coreboot files. | Martin Roth |
| 2016-07-28 | intel/fsp1_1: Add C entry support to locate FSP Temp RAM Init | Subrata Banik |
| 2016-07-28 | soc/intel/skylake: Add C entry bootblock support | Subrata Banik |
| 2016-07-28 | soc/intel/skylake: Do cache as ram and prepare for C entry | Subrata Banik |
| 2016-04-14 | soc/intel: Update license headers | Martin Roth |
| 2016-02-04 | intel/skylake: unconditionally set SPI controller BAR | Aaron Durbin |
| 2016-01-12 | intel/skylake: Remove check for Microcode loaded by ME | Martin Roth |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-10-15 | cpu/mtrr.h: Fix macro names for MTRR registers | Alexandru Gagniuc |
| 2015-10-11 | skylake: Leave SPI controller enabled | Lee Leahy |
| 2015-10-11 | skylake: SPI code cleanup | Lee Leahy |
| 2015-09-09 | x86: bootblock: remove linking and program flow from build system | Aaron Durbin |
| 2015-08-13 | skylake: fix garbled patch from upstream | Aaron Durbin |
| 2015-07-29 | Skylake: Fix microcode reload in bootblock cpu init | Rizwan Qureshi |
| 2015-07-16 | soc/intel: Add Skylake SOC support | Lee Leahy |
| 2015-07-16 | soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC | Lee Leahy |
