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path: root/src/soc/intel/skylake/bootblock/pch.c
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2017-11-15soc/intel/skylake: Make use of common CSE code for skylakeSubrata Banik
TEST=Ensures global reset could able to reset system. Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha
Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20499 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-03soc/intel/skylake: Enable common LPC IPRavi Sarawadi
Enable Skylake to use the new common LPC code. This will help to reduce code duplication and streamline code bring up. Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-11soc/intel/skylake: Fix PMC address range setup for PCH-HNico Huber
The PMC of PCH-H requires a different destination id. TEST=Run on kontron/bsl6 and observed that PM registers are correctly dumped at start of romstage. Change-Id: I862e4df986f1cdea34f8fa45d016fb6b51f29122 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-11soc/intel/skylake: Set generic I/O decode ranges earlyNico Huber
Move the generic I/O decode range setup before the console init. TEST=Run on kontron/bsl6 which requires 0xa80/0xa81 decoded to initialize serial ports. Serial console works from boot- block on. Change-Id: I9829f188c80eb73f6cd91b0c22e1c07da5745ad6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-09soc/intel/skylake: Use intel/common/block/smbus codeAamir Bohra
Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-02soc/intel/skylake: Clean up code by using common FAST_SPI moduleBarnali Sarkar
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19055 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-28soc/intel/skylake: Use ITSS common codeBora Guvendik
This patch uses common ITSS library to setup itss irq. Change-Id: Ibe65a92f1604277bec229c67f4375b6636c0972d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19244 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10soc/intel/skylake: Use RTC common codeSubrata Banik
This patch uses common RTC library to enable upper 128 byte bank of RTC RAM. Change-Id: Ibcbaf5061e96a67815116a9f7a03be515997be6d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-10soc/intel/skylake: Use common PCR moduleSubrata Banik
This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28soc/pci_devs.h: Use consistent naming in soc/pci_devs.hSubrata Banik
This patch to make common PCI device name between APL and SKL. Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-17soc/intel/skylake: Fix remaining issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: Macros with complex values should be enclosed in parentheses ERROR: "foo * bar" should be "foo *bar" ERROR: space required before the open parenthesis '(' ERROR: spaces required around that '=' (ctx:VxW) WARNING: space prohibited between function name and open parenthesis '(' WARNING: storage class should be at the beginning of the declaration WARNING: char * array declaration might be better as static const WARNING: please, no space before tabs WARNING: braces {} are not necessary for single statement blocks WARNING: else is not generally useful after a break or return WARNING: static const char * array should probably be static const char * const TEST=Build for glados Change-Id: Ic14ca3abd193cfe257504a55ab6b74782b26bf6d Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18868 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17soc/intel/skylake: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch: WARNING: line over 80 characters TEST=Build for glados Change-Id: I79341f46ca06ac052f987975ccaf975470d27806 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18867 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-11-30soc/skylake: Move IO decode range out from pch_lpc_initTeo Boon Tiong
1. Move existing IO decode range from pch_lpc_init to early stage before SIO init. 2. At the same time, enable SIO decode range (0x2e/0x2f) for platform which use super IO. Change-Id: I72df16d0a784686d8cadfbee09b5aef60576ac43 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17337 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-27skylake: Prepare GPE for use in bootblockDuncan Laurie
Export the pmc_gpe_init() function from pmc.c to pmutil.c so it can be used in bootblock, and then call it from there to initialize any GPEs for use in firmware. BUG=chrome-os-partner:58666 TEST=test working GPE as TPM interrupt on skylake board Change-Id: I6b4f7d0aa689db42dc455075f84ab5694e8c9661 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17135 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-16soc/intel/skylake: Enable HECI BAR for ME communicationSubrata Banik
This patch programs and enables BAR for ME (bus:0/ device:0x16/function:0) device to have early ME communication. BUG=none BRANCH=none TEST=Verified Global Reset MEI message can able to perform platform global reset during romstage. Change-Id: I99ce0ccd42610112a361a48ba31168c9feaa0332 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-18soc/intel/skylake: Move bootblock specific code from skylake/romstageNaresh G Solanki
There is a lot of code that is being referred to in bootblock but resides under skylake/romstage folder. Hence move this code into skylake/bootblock, and update the relevant header files and Makefiles. TEST=Build and Boot kunimitsu. Change-Id: If94e16fe54ccb7ced9c6b480a661609bdd2dfa41 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16225 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-18skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early initRizwan Qureshi
Prepare Skylake for FSP2.0 support. We do not use FSP-T in FSP2.0 driver, hence guard the FspTempRamInit call under a switch. In addition to the current early PCH configuration program few more register, so all in all we do the following, * Program and enable ACPI Base. * Program and enable PWRM Base. * Program TCO Base. * Program Interrupt configuration registers. * Program LPC IO decode range. * Program SMBUS Base address and enable it. * Enable upper 128 bytes of CMOS. And split the above programming into into smaller functions. Also, as part of bootblock_pch_early_init we enable decoding for HPET range. This is needed for FspMemoryInit to store and retrieve a global data pointer. And also move P2SB related definitions to a new header file. TEST=Build and boot Kunimitsu Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-28soc/intel/skylake: Add C entry bootblock supportSubrata Banik
List of activity performing in this patch - early PCH programming - early SA programming - early CPU programming - mainborad early gpio programming for UART and SPI - car setup - move chipset programming from verstage to post console BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x34 Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-04intel/skylake: unconditionally set SPI controller BARAaron Durbin
The setting of the SPI controller BAR was conditional on the nominal frequency being set. Therefore, that doesn't mean the SPI BAR is set on all boots. Move the setting of the BAR in the southbridge_bootblock_init() which is called prioer to cpu_bootblock_init(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Confirmed spibar is always set on glados. Change-Id: Ia58447d70f5e39a4336d4d08593f143332de833a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 56fff7c25c2eb0ccd90e08f71c064b83c66640f8 Original-Change-Id: I1e0cff783f4b072b80589a3a84703a262b86be3a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/319461 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13587 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy
Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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