coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-03-24	soc/intel/skylake: Use C entry code for MTRR programming	Subrata Banik
2017-03-06	soc/intel/skylake: Clean up CPU code	Subrata Banik
2016-08-18	soc/intel/skylake: Move bootblock specific code from skylake/romstage	Naresh G Solanki
2016-07-28	soc/intel/skylake: Add C entry bootblock support	Subrata Banik
2016-02-04	intel/skylake: unconditionally set SPI controller BAR	Aaron Durbin
2016-01-12	intel/skylake: Remove check for Microcode loaded by ME	Martin Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-15	cpu/mtrr.h: Fix macro names for MTRR registers	Alexandru Gagniuc
2015-10-11	skylake: Leave SPI controller enabled	Lee Leahy
2015-10-11	skylake: SPI code cleanup	Lee Leahy
2015-08-13	skylake: fix garbled patch from upstream	Aaron Durbin
2015-07-29	Skylake: Fix microcode reload in bootblock cpu init	Rizwan Qureshi
2015-07-16	soc/intel: Add Skylake SOC support	Lee Leahy
2015-07-16	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy