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Remove the Return statement within the PS0, PS3 methods. PS0/3 are not
allowed to return anything. Even an empty return will be resolved to
Return(Null). In order to be conform with the specification, the code
has been refactored to remove the return statements.
Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33293
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In PORTSC, Port Enabled/Disabled(PED) is RW1CS.
When there is a USB device attached on system, current UPWE method
will set 1 to PED, this will cause port disabled as it's RW1CS.
This change is inspired by xhci_port_state_to_neutral in linux driver.
It will mask all RO and RWS bits and set WDE and WCE.
BUG=b:70777816
TEST=System won't be awakend from s3 automatically when usb devices
is attached. Also system can be awakend by hotplugging usb
devices under S3.
Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Enable SS link trunk clock gating & D3hot when device enters
D3 state.
Similarly disable SS link trunk clock gating & D3hot when device enters
D0 state
TEST=Build & boot Poppy board. Check working for XHCI wake when DUT
is in S3.
Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18879
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Three things are required to enable wake-on-usb:
1. 5V to USB ports should be enabled in S3.
2. ASL file needs to have appropriate wake bit set.
3. XHCI controller should have the wake on attach/detach bit set for the
corresponding port in PORTSCN register.
Only part missing was #3.
This CL adds support to allow mainboard to define a bitmap in
devicetree corresponding to the ports that it wants to enable
wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in
PORTSCN would be set by xhci.asl for the appropriate ports.
BUG=chrome-os-partner:58734
BRANCH=None
TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb
attach/detach.
Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17056
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Updating to a new IASL introduces a lot of warnings that are
not serious issues but can be fixed with some reworks.
- Method local variables that are set but never used now warn,
when needing to read back a register the ordering is now changed
to set the value in Local0 first so the compiler does not complain.
- Methods that create an object must be serialized
- A ResourceTemplate declared inside a _CRS with a named variable
does not seem to be able to compile without a warning. To fix
this move the ResourceTemplate outside the _CRS method.
- The DPTF CPU code was still using the old legacy \_PR.CPUx
instead of the new \_PR.CPxx definitions.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build glados with iasl-20150717 and see no warnings
Original-Change-Id: I4a66c7eb6495aac4ae1aa42100c846725c1a04d2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302168
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia3af802ca2faab4f1c59e73f2ce31a65c7e862e0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11812
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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- Remove the old workarounds for XHCI from broadwell
- Add PMC device to expose bits needed for XHCI workarounds
- Implement the new workarounds for XHCI, the first will set
a bit in the XHCI MMIO and the second will send a message
to the PMC if a bit is set indicating the workaround is available.
- Clean up the HS/SS port defines and remove unnecessary
methods to determine the port count since we only support SPT-LP.
BUG=chrome-os-partner:44622,chrome-os-partner:44518
BRANCH=none
TEST=build and boot on glados, verify that D0 and D3 can be
made to work (by disabling unused USB and the misbehaving camera)
Change-Id: I535c9d22308c45a3b9bf7e4045c3d01481acc19c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a945f8bc2976d57373be2305c5da40a5691f1e88
Original-Change-Id: I7a57051c0a5c4f5408c2d6ff0aecf660100a1aec
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295950
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11537
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add the files to support the Skylake SOC.
Matches chromium tree at 927026db
BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform
Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use the Broadwell implementation as the comparison base for Skylake.
BRANCH=none
BUG=None
TEST=None
Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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