summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake/Makefile.inc
AgeCommit message (Collapse)Author
2015-09-08skylake: allow timer_monotonic_get() in all stagesAaron Durbin
The timer_monotonic_get() function wasn't being compiled for romstage. To simplify the implementation don't keep track of partial microsecond ticks and just return the MSR value divided by 24 (24MHz clock). BUG=chrome-os-partner:42115 BRANCH=None TEST=Build and booted glados. Used monotonic timers in romstage in subsequent patches. Change-Id: I8294c74abe09947fb4438bf5c1d0fc5265491694 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6d60ef204fc92c26748ab57d4ff37830cd8dc664 Original-Change-Id: Ibdb6b9e20b9f2d48ff0f8a8c782f5c1f7ddde4f7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295237 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11540 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/skylake: Implemented generic SPI driver for ROM/RAMSTAGE access.Subrata
Created generic library to implement SPI read, write, erase and read status functionality for both ROMSTAGE and RAMSTAGE access. BRANCH=NONE BUG=chrome-os-partner:42115 TEST=Built for sklrvp and kunimitsu and verify SPI read, write, erase success from ELOG. Change-Id: Idf4ffdb550e2a3b87059554e8825a1182b448a8a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 74907352931db78802298fe7280a39913a37f0c2 Original-Change-Id: Ib08da1b8825e2e88641acbac3863b926ec48afd9 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294444 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Subrata Banik <subrata.banik@intel.com> Original-Commit-Queue: Subrata Banik <subrata.banik@intel.com> Reviewed-on: http://review.coreboot.org/11422 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28soc/*/Makefile.inc: Do not add soc/common as a subdirAlexandru Gagniuc
Aaron Durbin found that soc/common is already included as a subdir via the wildcard in Makefile.inc: subdirs-y += $(wildcard src/soc/*/*) Since the entire file is protected by CONFIG_SOC_INTEL_COMMON, there is no problem with including it for every platform. On the other hand, when it is included by the skylake and braswell makefiles, any rule is duplicated. As a result fix the braswell and skylake makefiles. Change-Id: If5bad903c78dbce418852935ee55cdc7162b3b2d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11439 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-13skylake: fix serial port with new code baseAaron Durbin
Many Kconfig options changed in coreboot.org since skylake was first started. Fix Kconfig option name changes, and also provide a common option, UART_DEBUG that can be selected to select all the necessary options. Note: It's still a requirement to manually unset the 8250IO option because that's unconditionally set. BUG=chrome-os-partner:43419 BUG=chrome-os-partner:43463 BRANCH=None TEST=Built glados. Booted into kernel. Kernel reboots somewhere. Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289951 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11172 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy
Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>