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2016-06-12soc/intel/quark: Add C bootblockLee Leahy
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected. This is the first piece in supporting FSP 2.0. Move esraminit from romstage into the bootblock. Replace cache_as_ram with car_stage_entry.S and code in romstage.c TEST=Build and run on Galileo Gen2 Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15132 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09soc/intel/quark: Pass serial port address to FSPLee Leahy
Pass the serial port address to FSP using a UPD value in the MemoryInit API. TEST=Build and run on Galileo Gen2 Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15079 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31quark: Enable HSUART0 as consoleLee Leahy
The use of HSUART0 on galileo requires early initialization of the I2C GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1 on the expansion connector. TEST=None Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15010 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Move UART init into romstage.cLee Leahy
Move UART initialization into romstage.c and eliminate uart.c. TEST=Build and run on Galileo Gen2 Change-Id: I5f2c9b4c566008000c2201c422a0bba63da64487 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15009 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Split I2C out from driverLee Leahy
Split out the I2C code to allow I2C transactions during early romstage. TEST=Build and run on Galileo Gen2 Change-Id: I87ceb0a8cf660e4337738b3bcde9d4fdeae0159d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Set temporary I2C base addressLee Leahy
Set a temporary I2C base address during romstage. TEST=Build and run on Galileo Gen2 Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15006 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Conditionally define BIT namesLee Leahy
Only define BIT names if they are not already defined. TEST=Build and run on Galileo Gen2 Change-Id: Ief4c4bb7a42a1bb2a7f46f13dc9b8bbb4d233e3c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15002 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Fix reg_script displayLee Leahy
Remove extra ": " following reigster type. TEST=Build and run on Galileo Gen2 Change-Id: I57dd40a540d7b5371a6c45174f47a311b83a2aab Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14948 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Clear SMI interrupts and wake eventsLee Leahy
Migrate the clearing of the SMI interrupts and wake events from FSP into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14945 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Rename pmc.c to lpc.cLee Leahy
Rename the file pmc.c to lpc.c to prepare for further additions. TEST=Build and run on Galileo Gen2 Change-Id: If98825d72878f0601f77bff8c766276dbda8a9ae Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14946 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Add PCIe reset supportLee Leahy
Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into coreboot. Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14944 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-25soc/intel/quark: Add USB device port supportLee Leahy
Add initialization for the USB device port. TEST=Build and run on Galileo Gen2 Change-Id: Icf83747f778f6e1ac976cd448a94311030e79e4f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-23soc/intel/quark: Add EHCI errataLee Leahy
Move the EHCI errata from QuarkFSP into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I424ffd81643fbba9c820b5a8a6809b9412965f8d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14940 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-23soc/intel/quark: Rename usb.c to ehci.cLee Leahy
Rename usb.c to ehci.c since it contains EHCI specific content. TEST=Build and run on Galileo Gen2 Change-Id: Ifdb7cd937b1dffda1959b76e1c911ffd93f53cb6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14939 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-23soc/intel/quark: Switch reference from uart_dev to uart_bdfLee Leahy
Switch from using uart_dev to uart_bdf to better describe the value in use. TEST=Build and run on Galileo Gen2 Change-Id: If5066b93ea8ccce4a5b89ee3984c7413d5358e71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14938 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-18soc/intel/quark: Add I2C supportLee Leahy
Add the I2C driver. TEST=Build and run on Galileo Gen2 Change-Id: I53fdac93667a8ffb2c2c8f394334de2dece63d66 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14828 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Fix spelling errorLee Leahy
Change Memroy to Memory in comment. TEST=None Change-Id: Ic57fcf962be6a302dcd7b52b9256a182577e734b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14881 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Perform GPIO initializationLee Leahy
Set the base address and enable the GPIO and legacy GPIO controllers. Call the mainboard routine to initialize the GPIO controllers. TEST=Build and run on Galileo Gen2 Change-Id: I06aed5903d6655d2a0948fb544cf9e0db68faa26 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14827 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Add GPIO register accessLee Leahy
Add register access routines for the GPIO and legacy GPIO controllers. TEST=Build and run on Galileo Gen2 Change-Id: I0c023428f4784de9e025279480554b8ed134afca Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14825 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Add LPC symbolsLee Leahy
Add LPC_DEV and LPC_FUNC symbols TEST=Build and run on Galileo Gen2 Change-Id: I8485e2671af439f766228d4eaf9677c2ff8ff3f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14880 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Reformat include/soc/pci_devs.hLee Leahy
Replace # define with #define Align the right hand column to prepare for further expansion TEST=Build and run on Galileo Gen2 Change-Id: Ie4d9fb56d52d7291be5523d31c1d3aa51f94dcd6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14879 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Add Ioh.h from EDK-IILee Leahy
Add Ioh.h from EDK-II to enable easy comparisons between EDK-II and coreboot implementations. TEST=Build and run on Galileo Gen2 Change-Id: I9320101a4a2c16ed18f682f3d04623c54afb52fd Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14824 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-05-11soc/intel/quark/include/soc: Update the Intel licenseLee Leahy
Remove the phrase "which accompanies this distribution" from the license. Re-format the license to fit in 80 columns. TEST=Build and run on Galileo Gen2 Change-Id: I8d893cf1270b95b27eab7142b276ebfce24ec2ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14774 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09soc/intel/quark: Identify the console UARTLee Leahy
Pass the UART identifier to CorebootPayloadPkg Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: I9db1c31c3544d56b66f5a79ac8c3acee41788983 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-05soc/intel/quark: Add script time delay supportLee Leahy
Add time delay support to the scripts. TEST=Build and run on Galileo Gen2 Change-Id: I2c87977e2a2547e00769e59e1ee81fbbb5dff33f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14555 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-05soc/intel/quark: Add temperature sensor supportLee Leahy
Migrate the temperature sensor support from QuarkFspPkg into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I6dc68c735375c9d1777693264674521f67397556 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14565 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04soc/intel/quark: Add USB PHY initializationLee Leahy
Add register access support using register scripts. Initialize the USB PHY using register scripts. TEST=Build and run on Galileo Gen2 Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14496 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-03soc/intel/quark: Add IntelQNCConfig.h from EDK-IILee Leahy
Add the EDK-II Quark file IntelQNCConfig.h. This adds the definitions for the temperature sensor. TEST=Build and run on Galileo Gen2 Change-Id: I70896e6187b878ea572535432912f1d4db895a99 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14497 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-02soc/intel/quark: Remove UPD parametersLee Leahy
Remove the UPD parameters to match QuarkFsp code. TEST=Build and run on Galileo Gen2 Change-Id: Ie4639d1f087cc2bc4387aa691eb66b640fe8faf9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14451 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22soc/intel/quark: Fix MTRR readsLee Leahy
Remove offset override improperly added in the "Disable the ROM shadow" patch TEST=Build and run on Galileo Gen2 Change-Id: I32fb2da48e3769d59a49619539053f9afdf63b04 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14450 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22soc/intel/quark: Fix uninitialized variable d_variantLee Leahy
Initialize the d_variant variable. Found-by: CID 1353356 Uninitialized variable TEST=Build and run on Galileo Gen2 Change-Id: I26fba4e77f91d53b6ff9028669aa0186d3174639 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14338 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21soc/intel/quark: Disable the ROM shadowLee Leahy
Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing successful display of 0x000ffff0 - 0x000fffff does not match the end of the SPI flash. Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14110 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08soc/intel/quark: Set the UPD values for MemoryInitLee Leahy
Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13896 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-08soc/intel/quark: Add the UPD support for SiliconInitLee Leahy
Add the routines to handle the UPDs for SiliconInit. Currently no support is required. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful if coreboot calls SiliconInit Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-07soc/intel/quark: Split out MTRR supportLee Leahy
Split out the MTRR support into a new module: mtrr.c. TEST=Build and run on Galileo Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29soc/intel/quark: Reserve non-MMIO spaceLee Leahy
Adjust the memory map to allocate MMIO from non-memory addresses. TEST=None Change-Id: Icb6863665c466e8609af73eb9338165c7d6f46bf Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13856 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29soc/intel/quark: Initialize some of the FADT base registersLee Leahy
Initialize the base addresses for: * Power management control * Power management status * Reset * Power management timer * General-Purpose Event 0 Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when: * Register address are properly displayed by the payload * "reset -c" performs a reset and reboots the system * "reset -w" performs a reset and reboots the system * "reset -s" performs a reset and turns off the power Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13764 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22soc/intel/quark: Add the initial pieces required for ACPI tablesLee Leahy
Enable ACPI tables TEST=None Change-Id: I38b90f54cd9b00b063557c08980e71851bf3059b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13758 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19soc/intel/quark: Use single ID value for HSUART1Lee Leahy
Use single ID value for HSUART1. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Debug serial output stays enabled after BS_DEV_RESOURCES state Change-Id: I38eca247f151e67c2b243a8a3bb21d9d1f4603de Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13734 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18soc/intel/quark: Enable HSUART1Lee Leahy
Enable HSUART1 for debug serial output. Specify the fixed resources in the UART driver. This keeps debug serial output flowing during the rest of the device initialization. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Debug serial output stays enabled after BS_DEV_RESOURCES state Change-Id: Ica02e5fece156b21d4a3889284ca467d55c7880d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13730 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18soc/intel/quark: Establish the Memory MapLee Leahy
Add ramstage.h to define some of the common header files used by the drivers in ramstage. Add northcluster.c, the driver for the memory controller, which defines the memory map. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Memory map successfully displayed in BS_WRITE_TABLES state Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18soc/intel/quark: Enumerate the PCI devicesLee Leahy
Add the chip and domain support which enables the display of the vendor and device IDs for the PCI devices. Testing on Galileo: * Edit src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The PCI vendor and device IDs are displayed. Change-Id: I517dcafd83c7dd850bc3471f939d6804a05020c3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13719 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10soc/intel/quark: Report CPU infoLee Leahy
Decode the CPU variants and display the CPU info. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Successful if Quark X1000 is displayed Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13605 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10soc/intel/quark: Call FSP SiliconInitLee Leahy
Optionally relocate FSP into DRAM and then call FSP SiliconInit. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_FSP_ENTRY_POINTS" * Add "select DISPLAY_HOBS" * Optionally add "select RELOCATE_FSP_INTO_DRAM" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * FSP entry points are displayed and * The message "FspSiliconInit returned 0x00000000" is displayed and * The HOBs are displayed correctly and * The message "ERROR - Missing one or more required FSP HOBs!" is not displayed Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13631 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10soc/intel/quark: MTRR supportLee Leahy
Add the SoC specific routines to access the MTRR registers. These registers exist in the host bridge and are not accessible via the rdmsr/wrmsr instructions. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_MTRRS" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The message "FSP TempRamInit successful" is displayed Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13530 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10soc/intel/quark: FSP MemoryInit SupportLee Leahy
Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_HOBS" * Add "select DISPLAY_UPD_DATA" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * MemoryInit returns 0 (success) and * The the message "ERROR - Coreboot's requirements not met by FSP binary!" is not displayed Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13447 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09soc/intel/quark: Enable Serial PortLee Leahy
Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if serial output is present on HSUART1 at 115200 baud, 8-bit, no parity Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13445 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-08soc/intel/quark: Add TempRamInit supportLee Leahy
Successfully invoke TempRamInit from the FSP binary: * Don't relocate the FSP binary image * Copy the FSP binary into ESRAM * Specify Kconfig values to easily debug ESRAM and TempRamInit code * Specify the FSP binary file location * Specify the FSP binary image ID * Specify where in the flash image the FSP image must reside * Specify the FSP data file location * Specify where to place the FSP data file in the flash image * Specify where in the ESRAM the FSP image must reside Test 1 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select ENABLE_DEBUG_LED_FINDFSP" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Test 2 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Remove "select ENABLE_DEBUG_LED_FINDFSP" * Add "select ENABLE_DEBUG_LED_TEMPRAMINIT" * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13443 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-08soc/intel/quark: Enable ESRAMLee Leahy
The Quark SoC uses ESRAM instead of cache-as-RAM. This code requires that utils/xcompile/xcompile change the machine architecture from i686 to i586 to ensure that the Quark does not attempt to execute unsupported instructions: * Adjust Makefile.inc to add the RMU to the coreboot image * Add code to enable the ESRAM Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h file from the EDK2 tree (https://github.com/tianocore/edk2.git) to enable easy differences and correct issues in coreboot that were found in EDK2. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_RMU_FILE" * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Remove power from the board * Apply power to the board * Testing is successful if the SD LED is on indicating that the end of esram_init.inc was reached Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13440 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-04soc/intel/quark: Add minimal Quark SoC X1000 filesLee Leahy
Add the files for minimal Quark X1000 SoC support: * Declare pei_data structure * Declare sleep states and chipset_power_state structure * Specify top of memory * Empty FspUpdVpd.h file TEST=None Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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