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Add ESRAM display to FSP 1.1
TEST=Build and run on Galileo Gen2
Change-Id: Ia47b0bdba65606a7f0695332d298fc1e910b0e2f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18804
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix the errors detected by checkpatch and update the copyright dates.
TEST=Build and run on Galileo Gen2
Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18591
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add Kconfig values and early debugging code to better segment and debug
the early code in bootblock by using the SD LED as an indicator. Update
the help text for the debug Kconfig values to point to the various
failure locations.
TEST=Build and run on Galileo Gen2
Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/17985
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix the build issues with FSP 2.0:
* Remove struct from the various data structures.
* Properly display the serial port UPDs.
* Change chipset_handle_reset parameter type
BRANCH=none
BUG=None
TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug off) and run on
Galileo Gen2
Change-Id: Icae578855006f18e7e5aa18d2fd196d300d0c658
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16808
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Switch from passing FSP the serial port address to passing FSP the
serial port output routine. This enables coreboot to use any UART in
the system and also log the FSP output.
TEST=Build and run on Galileo Gen2
Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16105
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change the debug output levels for quark:
* Remove excess debug output
* Change BIOS_DEBUG to BIOS_SPEW - exception in report_platform.c
TEST=Build and run on Galileo Gen2
Change-Id: I37d7ed21a7fc4c92efeb5b71dd01922d7d4b9192
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Disable FSP output when CONFIG_DEFAULT_CONSOLE_LOGLEVEL is not set to 8
(BIOS_SPEW). Use the console log level to choose between the serial
port address and NULL and pass it to FSP for the serial port address.
TEST=Build and run on Galileo Gen2.
Change-Id: I5498aad218524c211082d85d0ae9aacaf08a80f6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16005
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add the pieces necessary to successfully build and run romstage using
the FSP 2.0 build. Because romstage is using postcar, add the postcar
pieces so that romstage can attempt to load postcar.
TEST=Build and run on Galileo Gen2
Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15866
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add the pieces necessary to successfully build and run bootblock using
the FSP 2.0 build.
TEST=Build and run bootblock on Galileo Gen2
Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.
TEST=Build and run on Galileo Gen2
Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change routine name from car_state_entry to car_stage_entry.
TEST=Build and run on Galileo Gen2
Change-Id: Ifd11db3fa711f2fe52ade1c6cde94f9be1f3a652
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15857
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Quark does not support the rdmsr and wrmsr instructions. In this case
use a SOC specific routine to support the setting of the MTRRs. Migrate
the code from FSP 1.1 to be x86 CPU common.
Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c. Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I034c083604892a5fa25dff3b50e327e0a885b021
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15683
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
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Specify the memory initialization parameters in
mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to
initialize memory.
TEST=Build and run on Galileo Gen2
Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15260
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the unused Kconfig values which specify the PDAT file, its
location and inclusion into the coreboot file system. Remove the code
in romstage which locates the pdat.bin file.
TEST=Build and run on Galileo Gen2
Change-Id: I397aa22ada6c073c60485a735d6e2cb42bfd40ab
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15205
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected.
This is the first piece in supporting FSP 2.0. Move esraminit from
romstage into the bootblock. Replace cache_as_ram with
car_stage_entry.S and code in romstage.c
TEST=Build and run on Galileo Gen2
Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15132
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Pass the serial port address to FSP using a UPD value in the MemoryInit
API.
TEST=Build and run on Galileo Gen2
Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15079
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The use of HSUART0 on galileo requires early initialization of the I2C
GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1
on the expansion connector.
TEST=None
Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15010
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Move UART initialization into romstage.c and eliminate uart.c.
TEST=Build and run on Galileo Gen2
Change-Id: I5f2c9b4c566008000c2201c422a0bba63da64487
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15009
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Set a temporary I2C base address during romstage.
TEST=Build and run on Galileo Gen2
Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Migrate the clearing of the SMI interrupts and wake events from FSP into
coreboot.
TEST=Build and run on Galileo Gen2
Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14945
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into
coreboot.
Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14944
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Switch from using uart_dev to uart_bdf to better describe the value
in use.
TEST=Build and run on Galileo Gen2
Change-Id: If5066b93ea8ccce4a5b89ee3984c7413d5358e71
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14938
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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Set the base address and enable the GPIO and legacy GPIO controllers.
Call the mainboard routine to initialize the GPIO controllers.
TEST=Build and run on Galileo Gen2
Change-Id: I06aed5903d6655d2a0948fb544cf9e0db68faa26
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14827
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add register access support using register scripts.
Initialize the USB PHY using register scripts.
TEST=Build and run on Galileo Gen2
Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14496
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the UPD parameters to match QuarkFsp code.
TEST=Build and run on Galileo Gen2
Change-Id: Ie4639d1f087cc2bc4387aa691eb66b640fe8faf9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14451
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove offset override improperly added in the "Disable the ROM shadow"
patch
TEST=Build and run on Galileo Gen2
Change-Id: I32fb2da48e3769d59a49619539053f9afdf63b04
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14450
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Initialize the d_variant variable.
Found-by: CID 1353356 Uninitialized variable
TEST=Build and run on Galileo Gen2
Change-Id: I26fba4e77f91d53b6ff9028669aa0186d3174639
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14338
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Testing successful display of 0x000ffff0 - 0x000fffff does not match
the end of the SPI flash.
Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14110
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Set the UPD values for MemoryInit.
* Update the FspUpdVpd.h file which specifies the parameters for
MemoryInit.
* Add the necessary values to chip.h to enable values to come from
the mainboard's devicetree.cb file
* Add the parameters to the mainboard's devicetree.cb file
* Locate the platform configuration database file (pdat.bin)
* Copy the data values from the chip_info structure into the UPDs
* Display the UPD values
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_DISPLAY_UPD_DATA=y
* Testing successful when the UPD data is displayed before the call to
MemoryInit
Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13896
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Split out the MTRR support into a new module: mtrr.c.
TEST=Build and run on Galileo
Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Decode the CPU variants and display the CPU info.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Successful if Quark X1000 is displayed
Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13605
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
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Add the SoC specific routines to access the MTRR registers. These
registers exist in the host bridge and are not accessible via the
rdmsr/wrmsr instructions.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_MTRRS"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The message "FSP TempRamInit successful" is displayed
Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13530
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
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Add a dummy fill_power_state routine so that execution is able to reach
FSP MemoryInit.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_HOBS"
* Add "select DISPLAY_UPD_DATA"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* MemoryInit returns 0 (success) and
* The the message "ERROR - Coreboot's requirements not met by FSP
binary!" is not displayed
Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13447
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Note that the BIST value is always zero as validated in
esram_init.inc
* The initial TSC value is currently not saved!
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if serial output is present on HSUART1 at
115200 baud, 8-bit, no parity
Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13445
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
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Successfully invoke TempRamInit from the FSP binary:
* Don't relocate the FSP binary image
* Copy the FSP binary into ESRAM
* Specify Kconfig values to easily debug ESRAM and TempRamInit code
* Specify the FSP binary file location
* Specify the FSP binary image ID
* Specify where in the flash image the FSP image must reside
* Specify the FSP data file location
* Specify where to place the FSP data file in the flash image
* Specify where in the ESRAM the FSP image must reside
Test 1 on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select ENABLE_DEBUG_LED_FINDFSP"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Test 2 on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Remove "select ENABLE_DEBUG_LED_FINDFSP"
* Add "select ENABLE_DEBUG_LED_TEMPRAMINIT"
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13443
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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The Quark SoC uses ESRAM instead of cache-as-RAM. This code requires
that utils/xcompile/xcompile change the machine architecture from i686
to i586 to ensure that the Quark does not attempt to execute unsupported
instructions:
* Adjust Makefile.inc to add the RMU to the coreboot image
* Add code to enable the ESRAM
Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
file from the EDK2 tree (https://github.com/tianocore/edk2.git) to
enable
easy differences and correct issues in coreboot that were found in EDK2.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_RMU_FILE"
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Remove power from the board
* Apply power to the board
* Testing is successful if the SD LED is on indicating that the end of
esram_init.inc was reached
Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13440
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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