coreboot.git - my copy of coreboot

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2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
	Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
	Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " \|egrep ":( /\.\/\$\|#\|;#\|-- \| \ )" \| cut -d: -f1 \|grep -v crossgcc \|grep -v gcov \| grep -v /elf.h \|grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. /") -# This file is part of a set of unofficial pre-commit hooks available -/ This file is part of coreboot / -# This file is part of msrtool. -/ This file is part of msrtool. / - This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. / - This file is part of the coreboot project. - /* This file is part of the coreboot project. / -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/ This file is part of the coreboot project / -/ This file is part of the coreboot project. / -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. / -/ This file is part of the ectool project. / - This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. / -## This file is part of the superiotool project. -/ This file is part of the superiotool project / -/ This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
	Used commands: perl -i -p0e 's\|\/\[\s].is free software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and\/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]version[\s]2[\s]of[\s]the[\s]License.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.[\s]\\/\|/ SPDX-License-Identifier: GPL-2.0-only /\|' $(cat filelist) perl -i -p0e 's\|\/\[\s].is[\s]free[\s]software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]either[\s]version[\s]2[\s]of[\s]the[\s]License,[\s]or[\s].at[\s]your[\s]option.[\s]any[\s]later[\s]version.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.[\s]\\/\|/* SPDX-License-Identifier: GPL-2.0-or-later /\|' $(cat filelist) perl -i -p0e 's\|\/\[\s].is[\s#]free[\s#]software[;:,][\s#]you[\s#]can[\s#]redistribute[\s#]it[\s#]and/or[\s#]modify[\s#]it[\s#]under[\s#]the[\s#]terms[\s#]of[\s#]the[\s#]GNU[\s#]General[\s#]Public[\s#]License[\s#]as[\s#]published[\s#]by[\s#]the[\s#]Free[\s#]Software[\s#]Foundation[;:,][\s#]either[\s#]version[\s#]3[\s#]of[\s#]the[\s#]License[;:,][\s#]or[\s#].at[\s#]your[\s#]option.[\s#]any[\s#]later[\s#]version.[\s#]This[\s#]program[\s#]is[\s#]distributed[\s#]in[\s#]the[\s#]hope[\s#]that[\s#]it[\s#]will[\s#]be[\s#]useful[;:,][\s#]but[\s#]WITHOUT[\s#]ANY[\s#]WARRANTY[;:,][\s#]without[\s#]even[\s#]the[\s#]implied[\s#]warranty[\s#]of[\s#]MERCHANTABILITY[\s#]or[\s#]FITNESS[\s#]FOR[\s#]A[\s#]PARTICULAR[\s#]PURPOSE.[\s#]See[\s#]the[\s#]GNU[\s#]General[\s#]Public[\s#]License[\s#]for[\s#]more[\s#]details.[\s]\\/\|/* SPDX-License-Identifier: GPL-3.0-or-later /\|' $(cat filelist) perl -i -p0e 's\|(\#\#)[\w].is free software[:;][\#\s]you[\#\s]can[\#\s]redistribute[\#\s]it[\#\s]and\/or[\#\s]modify[\#\s]it[\s\#]under[\s \#]the[\s\#]terms[\s\#]of[\s\#]the[\s\#]GNU[\s\#]General[\s\#]Public[\s\#]License[\s\#]as[\s\#]published[\s\#]by[\s\#]the[\s\#]Free[\s\#]Software[\s\#]Foundation[;,][\s\#]version[\s\#]2[\s\#]of[\s\#]the[\s\#]License.[\s\#]This[\s\#]program[\s\#]is[\s\#]distributed[\s\#]in[\s\#]the[\s\#]hope[\s\#]that[\s\#]it[\s\#]will[\#\s]be[\#\s]useful,[\#\s]but[\#\s]WITHOUT[\#\s]ANY[\#\s]WARRANTY;[\#\s]without[\#\s]even[\#\s]the[\#\s]implied[\#\s]warranty[\#\s]of[\#\s]MERCHANTABILITY[\#\s]or[\#\s]FITNESS[\#\s]FOR[\#\s]A[\#\s]PARTICULAR[\#\s]PURPOSE.[\#\s]See[\#\s]the[\#\s]GNU[\#\s]General[\#\s]Public[\#\s]License[\#\s]for[\#\s]more[\#\s]details.\s(# \n)\|\1 SPDX-License-Identifier: GPL-2.0-only\n\n\|' $(cat filelist) perl -i -p0e 's\|(\#\#)[\w].is free software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and\/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]version[\s]2[\s]of[\s]the[\s]License.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.\s(#* \n)\|\1 SPDX-License-Identifier: GPL-2.0-only\n\n\|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18	soc: Remove copyright notices	Patrick Georgi
	They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-26	soc,mb/intel: clean up remaining FSP2.0 socs/boards	Michael Niewöhner
	Remove CONFIG_...FSP2.0 based if-switches from FSP2.0-only socs/boards Change-Id: Iae92dc2e2328b14c78ac686aaf326bd68430933b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36279 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-30	intel/quark: Use common romstage entry	Kyösti Mälkki
	Change-Id: Ifb2adcdef7265d43cb2bf6886f126f1a17bf08a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30	intel/quark: Remove extra steps on entry to romstage	Kyösti Mälkki
	Change-Id: I9297d5b4f7c8ed703fb8772739531cdd7d5ca5f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-11	mb/intel/galileo: Drop the FSP1.1 option	Arthur Heymans
	This board is EOL and has FSP2.0 support, so drop the older version. Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2016-08-05	soc/intel/quark: Add FSP 2.0 romstage support	Lee Leahy
	Add the pieces necessary to successfully build and run romstage using the FSP 2.0 build. Because romstage is using postcar, add the postcar pieces so that romstage can attempt to load postcar. TEST=Build and run on Galileo Gen2 Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15866 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05	soc/intel/quark: Add FSP 2.0 boot block support	Lee Leahy
	Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build. TEST=Build and run bootblock on Galileo Gen2 Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03	soc/intel/quark: Prepare for FSP2.0 support	Lee Leahy
	Split the original contents of romstage.c into car.c, romstage.c and fsp1_1.c. TEST=Build and run on Galileo Gen2 Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12	soc/intel/quark: Add C bootblock	Lee Leahy
	Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected. This is the first piece in supporting FSP 2.0. Move esraminit from romstage into the bootblock. Replace cache_as_ram with car_stage_entry.S and code in romstage.c TEST=Build and run on Galileo Gen2 Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15132 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31	soc/intel/quark: Move UART init into romstage.c	Lee Leahy
	Move UART initialization into romstage.c and eliminate uart.c. TEST=Build and run on Galileo Gen2 Change-Id: I5f2c9b4c566008000c2201c422a0bba63da64487 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15009 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31	soc/intel/quark: Add PCIe reset support	Lee Leahy
	Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into coreboot. Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14944 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07	soc/intel/quark: Split out MTRR support	Lee Leahy
	Split out the MTRR support into a new module: mtrr.c. TEST=Build and run on Galileo Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10	soc/intel/quark: Report CPU info	Lee Leahy
	Decode the CPU variants and display the CPU info. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Successful if Quark X1000 is displayed Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13605 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-09	soc/intel/quark: Enable Serial Port	Lee Leahy
	Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if serial output is present on HSUART1 at 115200 baud, 8-bit, no parity Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13445 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-08	soc/intel/quark: Add TempRamInit support	Lee Leahy
	Successfully invoke TempRamInit from the FSP binary: * Don't relocate the FSP binary image * Copy the FSP binary into ESRAM * Specify Kconfig values to easily debug ESRAM and TempRamInit code * Specify the FSP binary file location * Specify the FSP binary image ID * Specify where in the flash image the FSP image must reside * Specify the FSP data file location * Specify where to place the FSP data file in the flash image * Specify where in the ESRAM the FSP image must reside Test 1 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select ENABLE_DEBUG_LED_FINDFSP" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Test 2 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Remove "select ENABLE_DEBUG_LED_FINDFSP" * Add "select ENABLE_DEBUG_LED_TEMPRAMINIT" * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13443 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-08	soc/intel/quark: Enable ESRAM	Lee Leahy
	The Quark SoC uses ESRAM instead of cache-as-RAM. This code requires that utils/xcompile/xcompile change the machine architecture from i686 to i586 to ensure that the Quark does not attempt to execute unsupported instructions: * Adjust Makefile.inc to add the RMU to the coreboot image * Add code to enable the ESRAM Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h file from the EDK2 tree (https://github.com/tianocore/edk2.git) to enable easy differences and correct issues in coreboot that were found in EDK2. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_RMU_FILE" * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Remove power from the board * Apply power to the board * Testing is successful if the SD LED is on indicating that the end of esram_init.inc was reached Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13440 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>