coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-10-22	intel: Use CF9 reset (part 2)	Patrick Rudolph
	Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also implement board_reset() as a "full reset" (aka. cold reset) as that is what was used here for hard_reset(). Drop soc_reset_prepare() thereby, as it was only used for APL. Also, move the global-reset logic. We leave some comments to remind us that a system_reset() should be enough, where a full_reset() is called now (to retain current behaviour) and looks suspicious. Note, as no global_reset() is implemented for Denverton-NS, we halt there now instead of issuing a non-global reset. This seems safer; a non-global reset might result in a reset loop. Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-30	soc/intel/quark: Fix FSP 2.0 build	Lee Leahy
	Fix the build issues with FSP 2.0: * Remove struct from the various data structures. * Properly display the serial port UPDs. * Change chipset_handle_reset parameter type BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug off) and run on Galileo Gen2 Change-Id: Icae578855006f18e7e5aa18d2fd196d300d0c658 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05	soc/intel/quark: Add FSP 2.0 boot block support	Lee Leahy
	Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build. TEST=Build and run bootblock on Galileo Gen2 Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>