coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-02-04	soc/intel: Add get_pmbase	Eugene Myers
	Originally a part of security/intel/stm. Add get_pmbase to the intel platform setup code. get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access. Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12	src: Add missing include <device/pci_ops.h>	Elyes HAOUAS
	Change-Id: Iae73fc1557fb310dacbbf8bc486dc3cc5249d9e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33526 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23	src: Add missing include 'console.h'	Elyes HAOUAS
	Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-01-06	device: Use pcidev_on_root()	Kyösti Mälkki
	Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-08-05	soc/intel/quark: Clean up debug output levels	Lee Leahy
	Change the debug output levels for quark: * Remove excess debug output * Change BIOS_DEBUG to BIOS_SPEW - exception in report_platform.c TEST=Build and run on Galileo Gen2 Change-Id: I37d7ed21a7fc4c92efeb5b71dd01922d7d4b9192 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16006 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-29	soc/intel/quark: Initialize some of the FADT base registers	Lee Leahy
	Initialize the base addresses for: * Power management control * Power management status * Reset * Power management timer * General-Purpose Event 0 Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when: * Register address are properly displayed by the payload * "reset -c" performs a reset and reboots the system * "reset -w" performs a reset and reboots the system * "reset -s" performs a reset and turns off the power Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13764 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22	soc/intel/quark: Add the initial pieces required for ACPI tables	Lee Leahy
	Enable ACPI tables TEST=None Change-Id: I38b90f54cd9b00b063557c08980e71851bf3059b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13758 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>