coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2024-09-26	soc/intel/ptl: Remove tcss_d3_hot_disable en config structure field	Jeremy Compostella
	This commit drops tcss_d3_hot_disable chip config as FSP is not exposing the same purpose UPD anymore starting with Panther Lake SoC. BUG=b:348678529 TEST=Build for fatcat Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d58 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-21	soc/intel/ptl: Remove usb2_port_reset_msg_en config structure field	Jeremy Compostella
	Similarly to what is done in Meteor Lake, the PortResetMessageEnable UPD can be set based on usb2_port[].type_c setting and therefore usb2_port_reset_msg_en is not necessary. BUG=b/348678529 TEST=Build for fatcat Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d57 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84429 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-21	soc/intel/ptl: Provide the TCSS port policy setting options	Jeremy Compostella
	Each TCSS port can be associated a setting via the tcss_cap_policy device tree field. The setting can be picked within five values listed by this commit. BUG=b/348678529 TEST=fatcat board build tcss_cap_policy[0]=TCSS_TYPE_C_PORT_FULL_FUN Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d56 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-13	soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage	Saurabh Mishra
	List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I61930726ad0c765bfa1d72c5df893262be884834 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-04	tree: Use boolean for skip_ext_gfx_scan	Elyes Haouas
	Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-16	soc/intel/ptl: Do initial Panther Lake SoC commit till romstage	Saurabh Mishra
	List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API 4. Ref: Processor EDS documents Panther Lake U/H 12Xe/H 4Xe External Design Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and Volume 2 of 2 #813030 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>