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In preparation to add a third option, have "Client" platforms select a
dedicated Kconfig option instead of the common "_BASE" option. Rewrite
the help texts to clarify what "Client" and "Server" mean, because the
terms refer to the type of silicon and not to the market segment. Some
uniprocessor (single-socket) servers are actually client platforms and
there are some multi-socket workstations based on a server platform.
Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Ported back from commit ceaf9d116949da68aa9c ("soc/intel/alderlake:
Allow possible options for MP Init")
This patch creates choice that lists all possible options to perform
MP Init as below for Intel Meteor Lake platform:
1. MTL_USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP
runs feature programming based and selects MP_SERVICES_PPI_V2 config.
2. MTL_USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP
init and feature programming) using native implementation.
Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot
is expected to run MP Init.
Refactor SoC code to allow required FSP UPD override based on
selected MP Init option.
Additionally, added `FIXME` comment to ensure Intel MTL FSP can bring
back SkipMpInit UPD in MTL to let coreboot override this UPD and ensure
independent MP Init flow.
BUG=b:219053812
TEST=Able to build google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic917e4e03e24d73190cfc72c6ed8e59af427bedf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65743
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables coreboot doing Multiprocessor Initialization (MP)
for Meteor Lake CPU using the native coreboot drivers and passes the
MP PPI data structure to let FSP to perform CPU feature programming
(anything that is restricted) as part of FSP-S.
Additionally, modify the kconfig inclusion order alphabetically.
BUG=b:219061518, b:219053812
TEST=Able to bring all APs from reset by coreboot and successfully
able to perform all CPU feature programming using MP PPI services.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic2781ee0b39e42aa579b72d3d4ee6586d5a89a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65742
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures Intel Meteor Lake can enable the X2APIC feature.
While debugging Intel Meteor Lake (MTL) based platforms it seems like
enabling `DEFAULT_X2APIC` runs into a hang while coreboot tries to
bring the application processors (APs) from reset using X2APIC mode.
[INFO ] LAPIC 0x10 switched to X2APIC mode.
...
[DEBUG] Attempting to start 3 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[ERROR] Not all APs checked in: 0/3.
[DEBUG] 0/3 eventually checked in?
[ERROR] MP initialization failure.
[ERROR] MP initialization failure.
Note: The AP bring up flow between XAPIC and X2APIC are the same
except the way to access those LAPIC registers. X2APIC expects to
access all LAPIC registers using MSR (base with 0x800).
The correct flow to enable X2APIC on MTL would be as follows:
1. Let BSP bring all APs in XAPIC mode.
[INFO ] LAPIC 0x10 in XAPIC mode.
...
[DEBUG] Attempting to start 3 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[INFO ] LAPIC 0x11 in XAPIC mode.
[INFO ] LAPIC 0x0 in XAPIC mode.
[INFO ] LAPIC 0x80 in XAPIC mode.
2. Call enable_x2apic() function on all CPUs (BSP and APs)
And at the end of #2 above, all cores will now switch to X2APIC
from XAPIC.
[INFO ] Initializing CPU #0
[DEBUG] CPU: vendor Intel device a06a0
[DEBUG] Clearing out pending MCEs
[INFO ] LAPIC 0x10 switched to X2APIC mode.
...
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #1
[DEBUG] CPU: vendor Intel device a06a0
[DEBUG] Clearing out pending MCEs
[INFO ] LAPIC 0x11 switched to X2APIC mode.
Note: Intel MTL FSP also follow the same steps for x2APIC enablement
while coreboot selects USE_INTEL_FSP_MP_INIT config instead
MP_SERVICES_PPI_V2.
BUG=b:219061518, b:219053812
TEST=Able to perform coreboot doing AP init with
DEFAULT_X2APIC_LATE_WORKAROUND config enabled without running into
any hang issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9c8fad6c46b15b5b08c9cc4ef53f2a6872bd0ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65741
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit e54a8fd43247d767f16a37f3e3150b2915d809bc (soc/intel/meteorlake:
Add entry for GSPI2 device) added an entry for the GSPI2 device in the
devicetree, but did not add any other entries. Ensure that the rest of
the code is aware of the GSPI2 device to avoid any problems.
Change-Id: Ib59bd289751bd96402c4adc61ffbee3bebe0edb0
Found-by: Coverity CID 1490681
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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This patch adds GSPI2 (PCI device B0:D18:F6) entry into the chipset.cb.
Additionally, increases `CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX` value
to include GSPI2 as well.
BUG=b:224325352
TEST=Able to build and boot Google/Rex platform.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I901128a1773fc6d2ba87e3e4972f45ad4a754d35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65675
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Google uses two digit GPIO pad numbers for internal GPIO references
and Intel has updated their GPIO naming schemes too (see the GPIO
implementation worksheet #641238) so use double digit GPIO pad numbers.
Format -
"GPP_%c%02d", gpio_group, gpio_pad_num
e.g.
GPP_A0 -> GPP_A00,
GPP_V2 -> GPP_V02,
GPP_C9 -> GPP_C09 etc.
BUG=b:238196741
TEST=Able to build meteorlake based google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ieb7569c1a35b08c0970a604ec7b4b91e6179dd28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65719
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This change aligns the Meteor Lake TCSS functions of pad configuration
and Thunderbolt authentication through the sideband access.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I393f6e1c7d322878cbb684cd95bfa2477195b23a
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add 0x7d55 as another ID for Meteor Lake graphics controllers.
TEST=Boot with MTL silicon to check coreboot log for DID2
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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This patch removes all instances of the `ADL` from Meteor Lake SoC
directory.
TEST=Able to build and boot Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8153b2070467beb582ce1f70be97272ce09ca04c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65667
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates IFD_CHIPSET kconfig value from `ifd2` to `mtl`.
TEST=Able to build and boot Google/Rex image on MTL emulation
platform.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I416f881bcbe3dd7494ead636d6b593366a51b31c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch enables X2APIC to avoid hang-ups due to
`Switching from X2APIC to XAPIC mode is not implemented.`
BUG=b:237924211 ([MTL-FSP][v2222.1] Lists of boot issue with MTL FSP)
TEST=Able to enable X2APIC on rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I58649a9a6c9c0ba86856f6aa5fb470e2ef774e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65617
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.
BUG=b:237263080
TEST=Able to build and boot MTL simics. Also, verified the FSP debug
log is using coreboot debug library as below:
Before:
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle
is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
With this code change:
[SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add definitions for the GPIO pins on Meteor Lake SoC,
as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following GPIO communities and GPIO groups:
Comm. 0: GPP_CPU, GPP_V, GPP_C
Comm. 1: GPP_A, GPP_E
Comm. 3: GPP_H, GPP_F, SPI0, VGPIO3
Comm. 4: GPP_S, JTAG
Comm. 5: GPP_B, GPP_D, VGPIO
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I7fe9654f22b074a9af18eb7bcdc21812dee77035
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64169
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.
BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Change-Id: Iebe3d38f50e202d75add88f336b5f3e9ba9f5a22
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64168
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Fill required FSP-S UPD to call FSP-S API
BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB
helps in improving overall boot time since it reduces hashing and
body loading time (~30ms).
Backport changes from commit hash 84532dae1 (soc/intel/alderlake:
Change VBOOT_HASH_BLOCK_SIZE to 4 KiB).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3784b99bf06e0c03d123f290a98a0b1e4528b8d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64792
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
BUG=b:224325352
TEST=Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63363
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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clcok ---> clock
Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add Meteor Lake SA device ID 0x7d14 (4+8, 15W).
BUG=b:224325352
TEST=Able to build MTL SoC and verified SA DID is now shown proper.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures the IP initialization being done as part of MTL
bootblock code is able to complete the bootblock phase without any
visible hang.
The re-ordering in the MTL bootblock SoC programming is required to
ensure the SA early initialization is taking place prior to
performing any PCI Read/Write operation (like P2SB bar enabling for
IOE die etc.).
Additionally, Fast SPI init takes place prior to enabling ROM caching
etc.
BUG=b:224325352
TEST= Able to build and start booting the MTL simics.
Without this change, the code execution is stuck as below:
[NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG] IGD: device id ffff (rev ff) is Unknown
[INFO ] PMC: Using default GPE route.
[INFO ] VBNV: CMOS invalid, restoring from flash
[ERROR] init_vbnv: failed to locate NVRAM
[EMERG] Cannot locate primary CBFS
Able to detect the Flash and reading the SPI flash layout in proper
with this change as below:
[NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG] IGD: device id ffff (rev ff) is Unknown
[INFO ] PMC: Using default GPE route.
[INFO ] VBNV: CMOS invalid, restoring from flash
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1804000.
[DEBUG] FMAP: base = 0x0 size = 0x2000000 #areas = 33
[DEBUG] FMAP: area RW_NVRAM found @ 112b000 (24576 bytes)
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.
Test=Boot MTL simics and check cbmem -c | grep 'CBFS: Found'
lists all stages.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5dc5d5b99003b59b2262bd1e4eb5ccb11d721195
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Base code is based of Intel Alder Lake SOC code.
List of changes:
1. Add required Meteor Lake SoC programming till bootblock
2. Include only required headers into include/soc
3. Include MTL-P related DID, BDF
4. Ref: Processor EDS documents
vol1 #621483, vol2 #640858
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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