coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2022-06-06	soc/intel/meteorlake: Refactor bootblock SoC programming code	Subrata Banik
	This patch ensures the IP initialization being done as part of MTL bootblock code is able to complete the bootblock phase without any visible hang. The re-ordering in the MTL bootblock SoC programming is required to ensure the SA early initialization is taking place prior to performing any PCI Read/Write operation (like P2SB bar enabling for IOE die etc.). Additionally, Fast SPI init takes place prior to enabling ROM caching etc. BUG=b:224325352 TEST= Able to build and start booting the MTL simics. Without this change, the code execution is stuck as below: [NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8) [DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz [DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018 [DEBUG] CPU: AES supported, TXT supported, VT supported [DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P [DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC [DEBUG] IGD: device id ffff (rev ff) is Unknown [INFO ] PMC: Using default GPE route. [INFO ] VBNV: CMOS invalid, restoring from flash [ERROR] init_vbnv: failed to locate NVRAM [EMERG] Cannot locate primary CBFS Able to detect the Flash and reading the SPI flash layout in proper with this change as below: [NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8) [DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz [DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018 [DEBUG] CPU: AES supported, TXT supported, VT supported [DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P [DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG] IGD: device id ffff (rev ff) is Unknown [INFO ] PMC: Using default GPE route. [INFO ] VBNV: CMOS invalid, restoring from flash [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1804000. [DEBUG] FMAP: base = 0x0 size = 0x2000000 #areas = 33 [DEBUG] FMAP: area RW_NVRAM found @ 112b000 (24576 bytes) [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-06	soc/intel/meteorlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB	Subrata Banik
	This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. Test=Boot MTL simics and check cbmem -c \| grep 'CBFS: Found' lists all stages. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5dc5d5b99003b59b2262bd1e4eb5ccb11d721195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-06	soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock	Ravi Sarawadi
	Base code is based of Intel Alder Lake SOC code. List of changes: 1. Add required Meteor Lake SoC programming till bootblock 2. Include only required headers into include/soc 3. Include MTL-P related DID, BDF 4. Ref: Processor EDS documents vol1 #621483, vol2 #640858 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>