coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-12-14	soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage	Sridhar Siricilla
2020-11-27	soc/intel/jasperlake: Enable VT-d and generate DMAR Table	Meera Ravindranath
2020-11-02	soc/intel/jasperlake: Set the GpioOverride configuration	Ronak Kanabar
2020-10-05	soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()	Nick Vaccaro
2020-10-05	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro
2020-08-18	soc/intel/jasperlake: Configure IPU based on devicetree	Maulik V Vaghela
2020-07-28	soc/intel/jasperlake: Simplify is-device-enabled checks	Felix Singer
2020-07-26	soc/intel/jasperlakelake: Rename pch_init() code	Usha P
2020-07-23	soc/intel/jasperlake: Add the SkipCpuReplacementCheck configuration	V Sowmya
2020-07-22	soc/intel/jasperlake: Move tco_configure to bootblock	Tim Wawrzynczak
2020-07-06	soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init	Maulik V Vaghela
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-12	soc/intel/jasperlake: Remove deprecated UPDs	Ronak Kanabar
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
2020-05-01	soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understa...	Subrata Banik
2020-05-01	soc/intel/jasperlake: fix args of dimm_info_fill() for dram_part_num	Marco Chen
2020-04-14	soc/intel/jasperlake: Allow mainboard to override DRAM part number	Marco Chen
2020-04-06	soc/intel/jasperlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-01	soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC	Aamir Bohra
2020-03-28	soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake	Aamir Bohra
2020-03-28	soc/intel/jasperlake: Add Jasper Lake SoC support	Aamir Bohra