coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-06-03	soc/intel/jasperlake: Update C-States info	Ronak Kanabar
2020-05-26	soc/intel/jasperlake: correct IRQ routing Jasper Lake	Ronak Kanabar
2020-05-18	soc/intel/jasperlake: Add function to display ME firmware status info	Krishna Prasad Bhat
2020-05-18	jasperlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-14	soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()	Furquan Shaikh
2020-05-14	soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G	Furquan Shaikh
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-05	soc/intel/jasperlake: Correct the EMMC PCR Port ID	Ronak Kanabar
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
2020-04-14	soc/intel/jasperlake: Allow mainboard to override DRAM part number	Marco Chen
2020-04-06	soc/intel/jasperlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-28	soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake	Aamir Bohra
2020-03-28	soc/intel/jasperlake: Add Jasper Lake SoC support	Aamir Bohra