coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2023-09-27	soc/intel/jasperlake: Set GPE_STS and GPE_EN register bases	Jonathon Hall
2023-01-18	soc/intel/jasperlake: Use common gpio.h include	Dinesh Gehlot
2021-09-23	soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers	Michael Niewöhner
2021-06-19	soc/intel/jasperlake: Add offsets for pad locking	Aseda Aboagye
2020-11-09	soc/intel/jasperlake: Correct GPIO pad sequence for community pad group	Maulik V Vaghela
2020-11-09	soc/intel/jasperlake: Update reserved GPIO names in gpio_soc_defs.h	Maulik V Vaghela
2020-09-21	src/soc/intel: Drop unneeded empty lines	Elyes HAOUAS
2020-08-18	soc/intel/jasperlake: Fix PMC_GPE_DW mapping	Meera Ravindranath
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-03-28	soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake	Aamir Bohra