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These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a follow-up patch to initial copy patch for Jasper Lake SoC.
Remove all Tiger Lake specfic code from Jasper Lake SoC code.
BUG=b:150217037
Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a copy patch from Tiger Lake SoC code.
The only changes done on top of copy is changing below configs:
1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY
2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY
3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY
We started with initial assumption that JSL and TGL can co-exist.
But now we see the SoC code in Tiger Lake is relying on too many
compile-time directives to make two SoCs co-exist. Some of the
differences are listed below:
-> Kconfig: Multiple Kconfig options using
if SOC_INTEL_{TIGERLAKE/JASPERLAKE}
-> GPIO: GPIO communities have their own differences.
This requires conditional checks in gpio.asl, gpio.c, gpio*.h,
pmc.h and gpio.asl
-> PCI IRQs: Set up differently for JSL and TGL
-> PCIe: Number of Root ports differ.
-> eMMC/SD: Only supported on JSL.
-> USB: Number of USB port are different for JSL and TGL.
-> Memory configuration parameters are different for JSL and TGL.
-> FSP parameters for JSL and TGL are different.
The split of JSL and TGL SoC code is planned as below:
1. Copy Tiger Lake SoC code as is, and change SoC Kconfig
to avoid conflicts with current mainboard builds.
2. Clean up TGL code out of copy patch done in step 1.
Make it JSL only code. The SoC config still kept as
SOC_INTEL_JASPERLAKE_COPY.
3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to
SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can
bind to SoC code from soc/intel/jasperlake. This step establishes
Jasper Lake as a separate SoC.
4. Clean up current JSL code from TGL code. This step establishes
Tiger Lake as a separate SoC.
BUG=b:150217037
Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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