coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-02-09	soc/amd,intel: Drop s3_resume parameter on FSP-S functions	Kyösti Mälkki
2020-12-30	soc/intel: hook up new gpio device in the soc chips	Michael Niewöhner
2020-09-28	soc/intel/common/block/lpc: add acpi name	Jonathan Zhang
2020-07-27	soc/intel/jasperlake: Invoke PCIe root port swapping	Karthikeyan Ramasubramanian
2020-07-07	soc/intel/{tiger,jasper}lake: Add IPU to soc_acpi_name	Tim Wawrzynczak
2020-06-07	soc/intel/jasperlake: Add JSL PMC as 'hidden' PCI device	Tim Wawrzynczak
2020-05-12	device/pci_device: Extract pci_domain_set_resources from SOC	Raul E Rangel
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-11	soc/intel/jasperlake: Add ACPI device name for Storage controllers	Karthikeyan Ramasubramanian
2020-04-10	Replace DEVICE_NOOP with noop_(set\|read)_resources	Nico Huber
2020-04-10	Drop unnecessary DEVICE_NOOP entries	Nico Huber
2020-04-06	soc/intel/jasperlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-02	Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`	Nico Huber
2020-03-28	soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake	Aamir Bohra
2020-03-28	soc/intel/jasperlake: Add Jasper Lake SoC support	Aamir Bohra