coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-11-29	soc/intel: Configure P2SB before other PCH controllers	Furquan Shaikh
2020-09-29	soc/intel/jasperlake: Add IGD, MCH Device ID	Krishna Prasad Bhat
2020-08-17	soc/intel/jasperlake: Add IGD Device ID	Krishna Prasad Bhat
2020-08-07	soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE	Subrata Banik
2020-08-05	{nb,soc}/intel: Use get_current_microcode_rev() for ucode version	Subrata Banik
2020-07-29	soc/intel/jasperlake: Clean up report_cpu_info() function	Usha P
2020-07-26	soc/intel/jasperlakelake: Rename pch_init() code	Usha P
2020-07-22	soc/intel/jasperlake: Move tco_configure to bootblock	Tim Wawrzynczak
2020-06-03	soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-06-02	{icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includes	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-28	soc/intel/jasperlake: Add new MCH device ids	Maulik V Vaghela
2020-04-06	soc/intel/jasperlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-28	soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake	Aamir Bohra
2020-03-28	soc/intel/jasperlake: Add Jasper Lake SoC support	Aamir Bohra