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2019-11-01soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/Subrata Banik
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpiSubrata Banik
This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and asks specific soc code to refer lpc.asl from common code block. Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather than LPC. TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS. Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36455 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01lib/cbmem_top: Add a common cbmem_top implementationArthur Heymans
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-31soc/intel/{cnl,icl,skl}: Fix multiple whitespace issueSubrata Banik
Change-Id: I1e3dc1bd36c5de4e58eef6a3ba8ccbde28fba64b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36465 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31soc/intel/{cnl,icl,skl}: Remove unused SMI opregionSubrata Banik
TEST=Able to build and boot Hatch and DE. Change-Id: I6d63c005873fc5d67b4a44f42bb436628d7c1dc3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36462 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31soc/intel/icelake: adapt FSP GOP param to match the other FSP2.0 platformsMichael Niewöhner
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I5993e64631f86ff0f9ae069e10b89df8bc4cd085 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-31soc/intel/icelake: Enable caching on SPI memory-mapped boot device ↵Subrata Banik
unconditionally Icelake platform doesn't support booting from any other media (like eMMC on APL/GLK platform) than only booting from SPI device and on IA platform SPI is memory mapped hence enabling temporarily cacheing on memory-mapped spi boot media. Also removed inclusion of unused header in cpu.c file TEST=Able to build and boot ICL DE board. Change-Id: I46d9ec054c4804ca756f2101085a55e91b5cc6f0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36431 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30soc/intel/common: move common memmap functionality from skl,icl,cnl,aplMichael Niewöhner
This moves common memmap functionality from skl,icl,cnl,apl to the common tree. Change-Id: I45ddfabeac806ad5ff62da97ec1409c6bb9e89ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28src/soc/intel: skl,cnl,icl: remove unneeded check in cbmem_top()Michael Niewöhner
As stated in CB:36334 cbmem_top() should not be called before memory is initialized. Therefore drop the check to see if MRC finished. Change-Id: I964a20a5e9aa69fdb75413c36a17d34b7ba00098 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36386 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28src: Remove unused '#include <cpu/cpu.h>'Elyes HAOUAS
Change-Id: Ibcb1cafe36c255b4c5bd0a4faeedb95e91048709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-26soc/intel: common,skl,cnl,icl: drop reserved mmio memory size calculationMichael Niewöhner
Remove the calculation of the Reserved Intel MMIO Memory size from systemagent and memmap, since it is not needed. The size is used in SA to calculate the space between cbmem_top and TSEG without DPR and Chipset Reserved Memory. Since this will always be equal to 0, the reservation will be skipped and TSEG, DPR and Chipset Reserved Memory will get reserved alltogether. By reading the code and pratical testing we figured out that: - TSEG - DPR - reserved - top_of_memory == 0 - TSEG - DPR - reserved == top_of_memory This means the whole block will never reserve anything because it is always 0. Hence the code can be removed for simplification. Tested successfully on X11SSM-F Change-Id: I0cc730551eb3a79c78a971b40056de8d029f4b82 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-26soc,mb/intel: clean up remaining FSP2.0 socs/boardsMichael Niewöhner
Remove CONFIG_...FSP2.0 based if-switches from FSP2.0-only socs/boards Change-Id: Iae92dc2e2328b14c78ac686aaf326bd68430933b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36279 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25soc/intel: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: I09fce1298794f30c1db699438204ac32ee9cb27d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36296 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiBV Sowmya
The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when FSP uses the same stack provided by coreboot. This patch updates it to 129KiB since the default value of DCACHE_BSP_STACK_SIZE must be the sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). BUG=b:140268415 TEST=Build and boot CML-Hatch. Change-Id: Icedff8b42e86dc095fb68deb0b8f80b2667cfeda Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36032 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-02soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-29soc/intel: Rename <intelblocks/chip.h>Kyösti Mälkki
The filename chip.h has a special purpose with the generation of static devicetree, where the configuration structure name matches the path to the chip.h file. For example, soc/intel/skylake/chip.h defines struct soc_intel_skylake_config. The renamed file did not follow this convention and the structure it defines would conflict with one defined soc/intel/common/chip.h if such is ever added. Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-16src/soc/intel/{common,cnl,skl,icl}: Move global reset req function to commonSridhar Siricilla
send_heci_reset_req_message() is defined in multiple places, hence move it to common code. TEST=Verified on CMLRVP/Hatch/Soraka/Bobba/Dragon Egg boards. Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35228 Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15src/soc: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: I80c92f744fb9a6c3788b8b9ba779deef76e58943 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33530 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12soc/intel/{cnl, icl}: Cache the TSEG regionSubrata Banik
This patch helps to save additional ~19ms of booting time in normal boot and s3 resume on CML-hatch. BUG=b:140008206 TEST=Verified normal boot time on CML-Hatch with latest coreboot Without this CL: Total Time: 929ms With this CL: (TSEG marked as WB) Total Time: 910ms For test marked TSEG as WP/WC: Total Time: ~920ms Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35026 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11intel/fsp2_0: Add help text for FSP_TEMP_RAM_SIZE KconfigSubrata Banik
For CML & ICL, FSP requires at least heap = 0x10000 and stack = 0x20000. Refer to FSP integration guide to know the exact FSP requirement. BUG=b:140268415 TEST=Build and boot CML-Hatch and ICL. Change-Id: Ic1463181b4a9dca136d00cb2f7e3cce4f7e57bd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35301 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28soc/intel: Move fill_postcar_frame to memmap.cKyösti Mälkki
Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c codeSubrata Banik
This patch includes common romstage code to setup the console and load postcar. Fix booting regression issue on all latest IA-SOC introduced by CB:34893 Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-26intel/car: Use common TS_START_ROMSTAGEKyösti Mälkki
This timestamp also got unintentionally removed from some boards as they were transformed to use common romstage entry. Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26lib/bootblock: Add simplified entry with basetimeKyösti Mälkki
This allows for minor optimization as num_timestamps becomes a constant zero for a function with local scope. The loop with calls to timestamp_add() gets removed from bootblock. Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15intel/smm: Define struct ied_header just onceKyösti Mälkki
Change-Id: I6fc083aa30d05c11c1b6db7b3facacf5ae857c92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15soc/intel: Rename some SMM support functionsKyösti Mälkki
Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15intel/ice,sky,cannon: Drop unused EMRR and UNCORE_EMRR codeKyösti Mälkki
There was no code present to call wrmsr with the data we prepared in the structs. The MSRS are already set up by FSP, just reference with the more recent names of PRMRR and UNCORE_PRMRR. Change-Id: Ib49e7af52e1170a1304975ff0ae63f99e106dffe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15soc/intel: Drop spurious includesKyösti Mälkki
Change-Id: I2fff107e38abdd34f2d80d4d258be4c429d371e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15mainboard/google: Fix indirect includesKyösti Mälkki
Change-Id: Ie79702efab519b16cff45ccad61b95e7d8c2fbac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34854 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15cpu/x86/smm: Define single smm_subregion()Kyösti Mälkki
At the moment we only have two splitting of TSEG, one with and one without IED. They can all use same implementation. Make configuration problems of TSEG region assertion failures. Rename file from stage_cache.c to tseg_region.c to reflect it's purpose. Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13cpu/x86: Separate save_state struct headersKyösti Mälkki
Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-11arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki
Almost all platforms force it on. Make it enabled by default but under user control to optionally disable it. Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09cpu/x86/smm: Drop SMI handler address from structKyösti Mälkki
Change-Id: Ib925b11ba269e0f3a9a0a7550705bf2a6794c5b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-09soc/intel: Drop pmc_soc_restore_power_failure()Nico Huber
Get rid of this function and its dangerous, weak implementation. Instead, call pmc_set_power_failure_state() directly from the SMI handler. Change-Id: I0718afc5db66447c93289643f9097a4257b10934 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel/{cnl,icl}: Use new power-failure-state APINico Huber
pmc_soc_restore_power_failure() is only called from SMM, so add `pmc.c` to the `smm` class. Once all platforms moved to the new API, it can be implemented in a central place, avoiding the weak- function trap. Change-Id: Ib13eac00002232d4377f683ad92b04a0907529f3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08soc/intel: Fix SMRAM base MSRKyösti Mälkki
Previous setting was correct but assumed SMI handler is always located at the beginning of TSEG. Break the assumption. Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34730 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Handle smm_subregion() failureKyösti Mälkki
The callers don't necessarily check return value of function. Make sure the parameters are not left uninitialised in that case. Change-Id: Ic02db2d35b2ec88506320e7df609940de4aef005 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34708 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Change smm_subregion() prototypeKyösti Mälkki
Do this to avoid some amount of explicit typecasting that would be required otherwise. Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-08lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07intel/icelake,skylake,cannonlake: Drop unused parameterKyösti Mälkki
Change-Id: I0900c3b893d72063cc8df5d8ac370cf9d54df17a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-05soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOCAamir Bohra
This implementation adds support to provide list of LPSS controllers for a canonlake and icelake platforms. It implements strong function of get_soc_lpss_controllers defined under intel common block lpss driver. Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-04soc/intel/common/block/uart: Update the UART PCI device referenceAamir Bohra
This implementation revises the UART PCI device reference in common UART driver. The SOC functions have been aligned to provide the UART PCI device reference using pcidev_path_on_root. The uart_get_device() return type is changed, and files in which it gets used are updated. Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-02soc/intel/common/pch: Move thermal kconfig selection into common/pchSubrata Banik
This patch moves SOC_INTEL_COMMON_BLOCK_THERMAL selection from respective soc/intel/{skl/cnl/icl} to common/pch/Kconfig. Change-Id: I7c9c8a87cfc5cb4c2fa8b215e56cc35c1f0cce28 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34650 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/icelake: Make use of common thermal code for ICLSubrata Banik
This patch ports CB:34522 and CB:33147 changes from CNL to ICL. TEST=Build and boot dragonegg Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34649 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25soc/intel: Guard remaining SA_DEV_ROOT definitionKyösti Mälkki
Prevent implicit cast to pointers. The compiler doesn't warn about the conversion from integer to pointer without a cast, because SA_DEV_ROOT is literally '0' and there seems to be an exception for that conversion. Change-Id: I64fc156e3b9f578414ad03a00edb7cf3e33205c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-25soc/intel/icelake: Add ENABLE_DISPLAY_OVER_EXT_PCIE_GFX kconfigSubrata Banik
This patch creates new kconfig option to bring display over external PCI based GFX card. This kconfig to select required kconfig which are not default selected by VGA_ROM_RUN to launch legacy oprom from pci based GFX card. Change-Id: I8ebde69e38defbe3321eb5e5bbd632c209ae2cd8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-07-21soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel: Fix chip_info for PCH_DEV_PMCKyösti Mälkki
Since PCH_DEVFN_PMC device is a PCI device that may be hidden from enumeration, use SA_DEVFN_ROOT instead to locate the SOC configuration. Change-Id: I4b5195827fb32ec1dbd0bd6c9e243f4f9a4775ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-18soc/intel: Use config_of()Kyösti Mälkki
Change-Id: I0727a6b327410197cf32f598d1312737744386b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
2019-07-18soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I53324603c9ece1334c6e09d51338084166f7a585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-17soc/intel: Fix regression with hidden PCI devicesKyösti Mälkki
Fix regression with commit 903b40a soc/intel: Replace uses of dev_find_slot() Platforms where FSP hides PCI devices before enumeration may halt with error message 'PCI: dev is NULL!'. The workaround here is to print an error message revealing the faulty source code function and revert to old behaviour of dev_find_slot(). Change-Id: I5eab3e7f1993b686103eaa257aacda379dc259fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34285 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16soc/intel/{cnl,icl}: Always use CAR NEM enhanced by defaultAngel Pons
The FSP_CAR option has additional configuration options whose default values result in boot failures. Since default values should always boot, default to the open-source CAR NEM Enhanced implementation instead. This also allows us to get rid of an unnecessary vendor-specific special case. Change-Id: I30b1808f91701c07dce6f1de08c213150e8a675a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34287 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-14soc/intel/icelake: Update FSP UPDs if IGD is disable in devicetreeSubrata Banik
This patch sets required FSP UPDs to skip IGD initialziation if devicetree has disable IGD. Change-Id: I34a02bff112f922cabd48c23bc76370892ec62d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33739 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-14soc/intel/icelake: Make use of PCH_DEVFN_HDA macroSubrata Banik
Change-Id: I3be530072a6981760e9fe31e43741b4b480d045e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-13cpu/x86: Move smm_lock() prototypeKyösti Mälkki
The function implementations are in local platform scopes. Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timerSubrata Banik
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer for better code sharing. Also ported CB:33512 for SPT and ICP PCH. Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-10soc/intel: Remove invalid smm_relocate stubsKyösti Mälkki
Remove the per-platform empty stubs, builds would just fail as there is no equivalent conditional for the smmrelocate.c file. Change-Id: Ie11f307b7bc5415bfdba6a2c66aed01b70d9f0e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-09arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki
This is only a qualifier between TSEG and ASEG. Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.hSubrata Banik
Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07soc/intel/icelake: Remove redundant gpio.c from Makefile.incSubrata Banik
Change-Id: Ibddc2363e9bfea9ae41e4807435acb2e788dcb93 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-07soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstageFurquan Shaikh
This change intentionally removes the definition of PCH_DEV_PMC from ramstage to avoid silent errors. This device gets hidden from PCI bus in FSP-S and hence dropped from the root bus by the resource allocator. In order to avoid incorrect references to the device, avoid defining it in ramstage where it known to return NULL. BUG=b:136861224 Change-Id: I4f69470ec80c7127a2b604ed2b1f794f5a63e126 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34120 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07soc/intel/icelake: Get rid of unused dev paramFurquan Shaikh
This change gets rid of unused dev param to pmc_set_afterg3. BUG=b:136861224 Change-Id: I861bb132acf113c9d306175b670bf4a1ff742c28 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-07soc/intel/icelake: Use SA_DEV_ROOT instead of PCH_DEV_PMCFurquan Shaikh
PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets removed from the root bus as leftover unused device. With change 903b40a8a46 ("soc/intel: Replace uses of dev_find_slot()"), all uses of dev_find_slot() were replaced by pcidev_path_on_root() which relies on scanning of root bus to find the requested device. Since PMC device is removed from the root bus, pcidev_path_on_root() returns NULL for it thus resulting in configuration being skipped for the PMC ultimately resulting in S3 failures. Since the PCH_DEV_PMC was just used to get to chip config, this change replaces the use of PCH_DEV_PMC with SA_DEV_ROOT. BUG=b:136861224 Change-Id: Id68db8382b7b98e8e2e4a65ded1a6fb3bd057051 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-06soc/intel/icelake: Fix outb orderLijian Zhao
Similar to CB:33940, fix outb orders. Change-Id: I1d35235abc7e02e6058f07809b738635861cc9e4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jackpot51@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-04soc/intel: Replace uses of dev_find_slot()Kyösti Mälkki
To call dev_find_slot(0, xx) in romstage can produce invalid results since PCI bus enumeration has not been progressed yet. Replace this with method that relies on bus topology that walks the root bus only. Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-04arch/x86: Adjust size of postcar stackKyösti Mälkki
With VBOOT=y && VBOOT_MEASURED_BOOT=y message digest will be allocated from the stack and 1 KiB reserve used with the recent platforms was no longer sufficient. The comment of LZMA scratchpad consuming stack was obsolete for postcar, so these can be reduced to same 4 KiB. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-02soc/intel/icelake: Disable HDA based on devicetreeSubrata Banik
Change-Id: I28c2beca4bc26ddb896e68886571ebdc82276b48 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-06-21soc/intel: Provide SPD manufacturer ID and module type to SMBIOSDuncan Laurie
The DIMM manufacturing ID was not being initialized and so the DIMMs were not described in SMBIOS tables properly. The module type can also be provided, but the SMBIOS code expects SPD module type values from DDR2 so the DDR3/4 values are adjusted before sending to SMBIOS. BUG=b:134897498 BRANCH=sarien TEST=dump and compare with dmidecode BEFORE: Type: DDR4 Manufacturer: Unknown (0) Form Factor: Unknown AFTER: Type: DDR4 Manufacturer: Hynix/Hyundai Form Factor: SODIMM Change-Id: Id673e08aa6e3dad196009c3c21a3dda2f40c9e42 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-13soc/intel/{cml, whl}: Add option to skip HECI disable in SMMSubrata Banik
This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD. Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13soc/intel/icelake: Replace PCI device LPC to ESPI as per EDSSubrata Banik
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same. This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block. Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2019-06-09soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirementAamir Bohra
1. Gfx stolen memory requirement for ICL GFX 2. Enable PeiGraphicsPeim support Change-Id: I22dd14249b7402873f1ac07bee164ee7bee36414 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31955 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLINGSubrata Banik
Skip GT specific programming in coreboot to support early parts without GT enable. Change-Id: I231e13367cbfbafbfb0cb4235487dbcbcae76820 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33189 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06src/soc/intel/common/smbios: Add addtional infos to dimm_infoChristian Walter
Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry. Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03soc/intel: Replace UART_BASE() and friends with a KconfigNico Huber
Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident on APL at least. It is used outside of soc/intel/ scope, e.g. to con- figure SeaBIOS. As we only ever configure a single UART for the coreboot console, we don't need different addresses for each possible UART. Which saves us a lot of code. Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-03soc/intel/{skl,cnl,icl}: Drop soc_uart_set_legacy_mode()Nico Huber
This is never called: The only calling path is guarded by both !DRIVERS_UART_8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the latter selects the former. If somebody figures out how this is supposed to be used, we can easily revive the implementation. Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33093 Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29src/soc: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-22post_code: add post code for hardware initialization failureKeith Short
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to detect or initialize a required hardware component. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-21soc/intel: Remove unused pointer argument in mca_configure()Subrata Banik
Change-Id: Iad3982d9db07a1f17ac39e87ff9c37956e40c258 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-20soc/intel/icelake: Make use of gpio_pm_configure()Subrata Banik
Provide option in chip.h to set dynamic local clock gating setting. BUG=b:130764684 TEST=Able to build and boot ICL. Change-Id: Ic30a490aadb8cc9c05a19a05533ab0196c69b7f1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-18soc/intel: Fill DIMM serial number from SPDDuncan Laurie
Fill the DIMM serial number field for SMBIOS from the saved SPD data that is returned by FSP. BUG=b:132970635 TEST=This was tested on sarien to ensure that SMBIOS type 17 filled the serial number from the DIMM: Handle 0x000B, DMI type 17, 40 bytes Memory Device Locator: DIMM-A Serial Number: 41164beb Change-Id: I85438bd1d581095ea3482dcf077a7f3389f1cd47 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-13soc/intel/{cannonlake,icelake}: Drop unused cbmem.c fileElyes HAOUAS
Change-Id: Ib9444f7797289c9b8250cfb16eb1c12dff867ec3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-02soc/intel/icelake: Correct the GPE DWx mapping for GPIO groupsSubrata Banik
This implementation corrects the GPE DWx mapping for GPIO groups. The assignments is done in GPIO MISCFG register for all GPIO communities. And configures the which GPIO communities get register as Tier1. Change-Id: I9c306d46e5194944def26c24cdb95f5ebada42b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-05-02soc/intel/icelake: Select FSP_M_XIPSubrata Banik
This patch ports CB:32275 changes from CNL to ICL. Ice Lake require that FSP-M component should be XIP. This change selects FSP_M_XIP so that the right arguments are passed into cbfstool when adding this component. Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32507 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02soc/intel/icelake: Move power_state functions to pmutil.cSubrata Banik
This patch ports CB:31787 and CB:31908 changes from CNL to ICL. This change moves soc_fill_power_state and soc_prev_sleep_state to pmutil.c. It allows the functions to be used across romstage and smm. Also fix GEN_PMCON bit checks as below: ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A and so this change updates the check for these bits to use GEN_PMCON_A instead of GEN_PMCON_B. Change-Id: Ib7ab95b7bbcc97a076d27a11db2105f7b976b521 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32506 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02soc/intel/icelake: Add chipset event loggingSubrata Banik
This patch ports CB:30718 and CB:31908 changes from CNL to ICL. Add logging of chipset events on boot into the flash event log. This was tested on a google/dragonegg board to ensure that events like "System Reset" are added to the log as expected. Also fix GEN_PMCON bit checks as below: ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A and so this change updates the check for these bits to use GEN_PMCON_A instead of GEN_PMCON_B. Change-Id: I25ec32e81f8801f8d5e69c6095ffed73d75dded6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-05-02soc/intel/icelake: Clear PMCON status bitsSubrata Banik
This patch ports CB:31902 changes from CNL to ICL. The prev_sleep_state value was showing 5 even after warm reboot, once the SUS_PWR_FLR bit is being set. This bit was not being cleared. Hence clearing the PMCON status bits. Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32503 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-30vboot: refactor OPROM codeJoel Kitching
The name OPROM is somewhat inaccurate, since other steps to bring up display and graphics are needed depending on mainboard/SoC. This patch cleans up OPROM code nomenclature, and works towards the goal of deprecating vboot1: * Rename CONFIG_VBOOT_OPROM_MATTERS to CONFIG_VBOOT_MUST_REQUEST_DISPLAY and clarify Kconfig description * Remove function vboot_handoff_skip_display_init * Remove use of the VbInit oflag VB_INIT_OUT_ENABLE_DISPLAY * Add |flags| field to vboot_working_data struct * Create VBOOT_FLAG_DISPLAY_REQUESTED and set in vboot_handoff BUG=b:124141368, b:124192753, chromium:948529 TEST=make clean && make test-abuild TEST=build and flash eve device; attempt loading dev/rec modes BRANCH=none Change-Id: Idf111a533c3953448b4b9084885a9a65a2432a8b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29soc/intel: Add GPI interrupt config register offset infoKarthikeyan Ramasubramanian
Add the offset information for GPI interrupt status and enable register in the pad_community structure. Populate the concerned information for individual SoCs. This offset information is required to clear the interrupt configuration during the bootup. BUG=b:130593883 BRANCH=None TEST=Ensure that the interrupt configuration are cleared during bootup. Ensured that the system boots to ChromeOS. Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-26soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-13soc/intel/cpulib: Remove redundent enable/disable functionsSubrata Banik
This patch removes multiple enable/disable function definitions and make use of single function with argument to know feature status (enable/disable). Change-Id: I502cd2497b07e9de062df453ecbb9c11df692f5a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32282 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 00:27:22 +0000