coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-07-09	arch/x86: Flip HAVE_MONOTONIC_TIMER default	Kyösti Mälkki
2019-07-09	cpu/x86: Flip SMM_TSEG default	Kyösti Mälkki
2019-06-13	soc/intel/{cml, whl}: Add option to skip HECI disable in SMM	Subrata Banik
2019-06-03	soc/intel: Replace UART_BASE() and friends with a Kconfig	Nico Huber
2019-05-02	soc/intel/icelake: Select FSP_M_XIP	Subrata Banik
2019-04-30	vboot: refactor OPROM code	Joel Kitching
2019-03-19	soc/intel/icelake: Enable support for FSP 2.1 specification	Subrata Banik
2019-01-10	Untangle CBFS microcode updates	Nico Huber
2019-01-09	soc/intel: Clean mess around UART_DEBUG	Nico Huber
2019-01-08	soc/intel/icelake: Increase bootblock size	Subrata Banik
2018-11-22	soc/intel/icelake: Create macros for FSP consumption	Subrata Banik
2018-11-02	soc/intel/icelake: Allow coreboot to reserve stack for fsp	Aamir Bohra
2018-10-27	soc/intel/*: Make FSP header path user configurable	Patrick Georgi
2018-10-26	soc/intel/icelake: Do initial SoC commit	Aamir Bohra