aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/fsp_broadwell_de/Kconfig
AgeCommit message (Collapse)Author
2019-01-17soc/intel/fsp_broadwell_de: Enable FIT supportPatrick Rudolph
* Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Tested on wedge100s. Microcode is placed in FIT. Change-Id: Ie0003f597aa5f272847b4f8895a1e3571caa3464 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30956 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-15vendorcode/intel/fsp1_0/broadwell_de: Use FSP from 3rdparty/fspPatrick Rudolph
Default to FSP binary and headers shiped in 3rdparty/fsp. * Drop headers and code from vendorcode/intel/fsp1_0/broadwell_de * Select HAVE_FSP_BIN to build test the platform * Fetch FSP repo as submodule * Make FSP_HEADER_PATH known from FSP2.0 useable on FSP1.0 * Introduce FSP_SRC_PATH for FSP source file * Add sane defaults for FSP_FILE Tested on wedge100s. Change-Id: I46f201218d19cf34c43a04f57458f474d8c3340d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-10soc/intel/fsp_broadwell_de: Drop MICROCODE_BLOB_NOT_HOOKED_UPNico Huber
It's been hooked up in the meantime. Change-Id: I64176b09e375034189000ea4308c58771f0019a1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30812 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10Untangle CBFS microcode updatesNico Huber
The option to specify a binary file name was added later for platforms that do not provide microcode updates in our blobs repository. Alas, it wasn't visible what platforms these are. And if you specified a file for a platform that already had one, they were all included together. Make it visible which platforms don't provide binaries with the new con- figs MICROCODE_BLOB_NOT_IN_BLOB_REPO, MICROCODE_BLOB_NOT_HOOKED_UP and MICROCODE_BLOB_UNDISCLOSED. Based on that we can decide if we want to include binaries by default or explicitly show that no files are inclu- ded (default to CPU_MICROCODE_CBFS_NONE). Also split CPU_MICROCODE_CBFS_GENERATE into the more explicit CPU_MICROCODE_CBFS_DEFAULT_BINS and CPU_MICROCODE_CBFS_EXTERNAL_BINS. And clean up the visibility of options: Don't show CBFS related options on platforms that don't support it and don't show external file options if the platform uses special rules for multiple files (CPU_MICROCODE_ MULTIPLE_FILES). Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29934 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-22soc/intel/fsp_broadwell_de: Select RELOCATABLE_RAMSTAGEArthur Heymans
Tested on wedge100s. Change-Id: I0dcbce230c151cecbbbeec581964cd5f44fbe046 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29911 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21soc/intel/fsp_broadwell_de: Add vboot supportPhilipp Deppenwiese
Enable vboot2 in romstage. Change-Id: I7f1a1e8538999c5e4e54f3a4aa0cdf6d8a309c4f Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16fsp_broadwell_de: Switch to common SPI controller driverWerner Zeh
The common SPI controller driver in src/southbridge/intel/common does match the SPI controller included in the PCH of Broadwell-DE SoC. Switch to the usage of this driver and delete the dedicated one for the FSP based Broadwell-DE implementation. TEST: Boot mc_bdx1 with SPI driver active in romstage Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/29633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-10-22intel: Use CF9 reset (part 1)Patrick Rudolph
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
Bounce buffers used to be used in those cases where the payload might overlap coreboot. Bounce buffers are a problem for rampayloads as they need malloc. They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig The first three are obsolete or at least could be changed to avoid the need to have bounce buffers. The last two should change to no longer need them. In any event they can be fixed or pegged to a release which supports them. For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the value needed in 1999 for the 32-bit Linux kernel, the original ramstage) to 0xe00000 (14 Mib) which will put the non-relocatable x86 ramstage out of the way of any reasonable payload until we can get rid of it for good. 14 MiB was chosen after some discussion, but it does fit well: o Fits in the 16 MiB cacheable range coreboot sets up by default o Most small payloads are well under 14 MiB (even kernels!) o Most large payloads get loaded at 16 MiB (especially kernels!) With this change in place coreboot correctly still loads a bzImage payload. Werner reports that the 0xe00000 setting works on his broadwell systems. Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-13src/*/intel/: clarify Kconfig options regarding IFDStefan Tauner
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid Inter Flash Descriptor to exist. It does *not* identify platforms or boards that are capable of running in descriptor mode if it's valid. Refine the help text to make this clear. Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply declare that IFD is supported by the platform. Select this value everywhere instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected. Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to the mainboard directory. Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-07fsp_broadwell_de: enable spi consoleOkash Khawaja
this enables spi console for wedge100s with broadwell_de. the console size is 64kb. enabling spi console in `board.fmd` enables code which calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and `udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE` in fsp_broadwell_de's Kconfig to satisfy that. Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8 Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com> Reviewed-on: https://review.coreboot.org/28528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-13fsp_broadwell_de: Increase CONFIG_MAX_CPUS to 32Samuel Jimenez
Fix to accomodate for boards with more than 16 cores. Change-Id: I35b61d94491c21ef76717f761e566ca815880f27 Signed-off-by: Samuel Jimenez <aerojsam@gmail.com> Reviewed-on: https://review.coreboot.org/27847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06arch/x86: Always select RELOCATABLE_MODULESKyösti Mälkki
All boards except those with NO_RELOCATABLE_RAMSTAGE or explicit select already had this feature built. Change-Id: I838e12141243ec49c2555c09269e07476eb0cfad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06arch/x86: Flag platforms without RELOCATABLE_RAMSTAGEKyösti Mälkki
To flip the Kconfig default, flag some platforms with NO_RELOCATABLE_RAMSTAGE. Change-Id: I72c6d07e5a60789bbe0e068a0130d7e3bd07a1d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-28fsp_broadwell_de: Select TSC_MONOTONIC_TIMER by defaultDavid Hendricks
This is currently selected by each derivative board's Kconfig even though it's really an SoC-specific option. Change-Id: Iad135261915a0857c53c18aaebde7e46c97a8f40 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/26344 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-04-28fsp_broadwell_de: Add SMM codeWerner Zeh
Add basic SMM support for Broadwell-DE SoC. The code is mainly based on the SMM implementation of Broadwell with a few differences: - EMRR is now called PRMRR and the UNCORE part of it is not available - SMM_FEATURE_CONTROL is no longer a MSR but is now located in PCI space - currently only SERIRQ-SMI has a handler Change-Id: I461a14d411aedefdb0cb54ae43b91103a80a4f6a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19145 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-30soc/intel/fsp_broadwell_de/uart: Drop itNico Huber
A copy of our uart8250io driver sneaked in with Broadwell-DE support. The only difference is the lack of initialization (due to FSP handling that). TEST=manually compared resulting object files Change-Id: I09be10b76c76c1306ad2c8db8fb07794dde1b0f2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16786 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-13fsp_broadwell_de: Add Kconfig switch for SERIRQ operation modeWerner Zeh
The serial IRQ (SERIRQ) used by the LPC interface can operate either in continuous or in quiet mode. Add a Kconfig switch to select the desired mode. This switch can now be used on mainboard level to enable the needed mode per mainboard. Change-Id: Ibe246b88164a622f9c71ebe7bab752a083a49a62 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16575 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-15soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Iecd94494cb568b20bdf6649b46a9a9586074bdc7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15672 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-04-17broadwell_de_fsp: Select HAVE_INTEL_FIRMWAREWerner Zeh
By selecting this switch in Kconfig one can build complete rom image including descriptor and ME/TXE. Change-Id: I7307695008df9a61baba1eb024f1f48be62c53c8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14376 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-14soc/intel: Add Broadwell-DE SoC supportYork Yang
Initial files to support Broadwell-DE SoC. This is FSP 1.0 based project and is based on Broadwell-DE Gold release. Change has been verified on Intel Camelback Mountain CRB. Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: https://review.coreboot.org/14014 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-20 13:28:55 +0000