coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-03-26	soc/intel/fsp_baytrail: transition away from device_t	Antonello Dettori
	Replace the use of the old device_t definition inside soc/intel/fsp_baytrail. Change-Id: I2791346289c04049e6f032c8e120e4be9ba6657f Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17319 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-31	src/soc: Capitalize CPU, ACPI, RAM and ROM	Elyes HAOUAS
	Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-15	soc/intel/fsp_baytrail: use common Intel ACPI hardware definitions	Aaron Durbin
	Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I1ff1517ded2d43e3790d980599e756d0d064f75c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15674 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-06	PCI: Use PCI_DEVFN macro instead of DEV_FUNC	Werner Zeh
	There are several different macros available to convert a PCI device and function to a single 8 bit value. One is PCI_DEVFN and is defined in device/pci_def.h. The other is DEV_FUNC and is defined in several intel fsp based chipset implementations. In fsp_broadwell_de DEV_FUNC is even used without being defined at all. This patch unifies the situation so that only PCI_DEVFN is used. Change-Id: Ia1c6d7f3683badc66d15053846936d88aa836632 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-07	intel/fsp_baytrail: use 20K PU/PD for GPIO	Ben Gardner
	The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs. The 10K and 40K values map to 'reserved'. This brings the code closer to the non-FSP baytrail. Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/13907 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22	fsp_baytrail: Add full support for iosf access in reg_script	Werner Zeh
	Add all needed functions to fsp_baytrail so that reg_script can do full iosf access. To keep it simple, this patch synchronises iosf access between baytrail and fsp_baytrail. Change-Id: Ic7f52d7d90c0fe3560fa5a5d96f7fc15062d66d1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16	intel/fsp_baytrail: rename include folder baytrail to include/soc	Ben Gardner
	This is to match the layout of the non-fsp baytrail to make comparisons easier and possibly remove duplicate files. Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12686 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>