| Age | Commit message (Collapse) | Author |
|---|
|
1. Update SA base address & size
2. Update GBE control bit register value
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Update ABase, PMC GPIO value sets and PMC register base address.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Iba43b791cab0665ddebfbed68b7e2d15406ad206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
1. Add CPU, SA, PCH & IGD DIDs table into report_platform.c
2. Add additional EHL SA DID in pci_ids.h
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I5c98089873b17f82560eba13c7de3353b6d3e249
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Clone entirely from Jasperlake
List of changes on top off initial jasperlake clone
1. Rename from jasperlake to elkhartlake
2. Remove irelevant devices asls (ipu,ish,camera clock,gpio_op)
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I5e77081d1673cc0ca97edc63e9996c045ab6e9b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44812
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Clone entirely from Jasperlake
List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jsp" with "mcc"
4. Rename structure based on Jasperlake with Elkhartlake
5. Clean up upd override in fsp_params.c will be added later
6. Sort #include files alphabetically as per comment
7. Remove doc details from espi.c until it is ready
8. Remove pch_isclk & camera clocks related codes
9. Add new #define NMI_STS_CNT & NMI_EN as per comment
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Clone entirely from Jasperlake
List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Rename structure based on Jasperlake with Elkhartlake
4. Clean up upd override in fsp_params.c, will be added later
5. Temporarily remove _weak attributes in fsp_param & romstage.c
6. Add required headers into include/soc/ from jasperlake directory
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If2bbe0b8a12bb78b3650f9d0a60f002f7eacb513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
|
|
Clone entirely from Jasperlake
This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/36550
List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Rename structure based on Jasperlake with Elkhartlake
6. Add required headers into include/soc/ from JSL directory
Elkhart Lake specific changes will follow in subsequent patches.
1. soc/intel/elkhartlake: Update Kconfig
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9f91c1efa81a358b1f59e032e209e07b62d54613
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
