coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-02-16	soc/intel/elkhartlake: Remove unused <string.h>	Elyes HAOUAS
	Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\\|memcpy\\|memmove\\|memset\\|memcmp\\|memchr\\|strdup\\|strconcat\\|strnlen\\|strlen\\|strchr\\|strncpy\\|strcpy\\|strcmp\\|strncmp\\|strspn\\|strcspn\\|strstr\\|strtok_r\\|strtok\\|atol\\|strrchr\\|skip_atoi\\|snprintf' -- src/)\|grep '<' Change-Id: I66a288df5c10c3ee5b9df599edc02aaed9a334e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-15	soc/intel: Remove unused <console/console.h>	Elyes HAOUAS
	Change-Id: I630b7b0b1d564bcd99358caaaef4afd78c22866c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50528 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01	soc/intel/elkhartlake: Config PlatformDebugConsent	Frans Hendriks
	UPD PlatformDebugConsent field is not configured. The config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT is available but not used. Use this config value for PlatformDebugConsent. BUG= N/A TEST= Build Intel Elkhart Lake Change-Id: I697fb611dfb23e107fa8ef1543424b9797a7d027 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50108 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10	soc/intel/elkhartlake: Fix EHL mainboard build fail errors	Tan, Lean Sheng
	When EHL initial mainboard patch is uploaded, there are some build errors caused by EHL soc codes. Here are the fixes: 1. include gpio_op.asl to resolve undefined variables in scs.asl 2. remove unused variables in fsp_params.c 3. rearrage sequences of #includes to fix build dependency of soc/gpio_defs.h in intelblocks/gpio.h 4. add the __weak to mainboard_memory_init_params function 5. add the missing _len as per this patch changes https://review.coreboot.org/c/coreboot/+/45873 Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47804 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05	soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()	Nick Vaccaro
	Consolidate all weak declarations of mainboard_get_dram_part_num() to instead use the common definition in lib/spd_bin.c. BUG=b:168724473 TEST="emerge-volteer coreboot && emerge-nocturne coreboot && emerge-dedede coreboot" and verify build succeeds without error. Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro
	Change mainboard_get_dram_part_num() to return a constant character pointer to a null-terminated C string and to take no input parameters. This also addresses the issue that different SOCs and motherboards were using different definitions for mainboard_get_dram_part_num by consolidating to a single definition. BUG=b:169774661, b:168724473 TEST="emerge-volteer coreboot && emerge-dedede coreboot && emerge-hatch coreboot" and verify build completes successfully. Change-Id: Ie7664eab65a2b9e25b7853bf68baf2525b040487 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45873 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05	soc/intel/elkhartlake: add __weak to mainboard_get_dram_part_num()	Nick Vaccaro
	Add missing __weak declaration to Elkhart Lake's definition of mainboard_get_dram_part_num(). BUG=b:169774482, b:168724473 TEST=none Change-Id: I883d662315a9ab91eb6183ebcdfd7e7cc8064c64 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45871 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31	soc/intel/elkhartlake/romstage: Do initial SoC commit till romstage	Tan, Lean Sheng
	Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 4. Clean up upd override in fsp_params.c, will be added later 5. Temporarily remove _weak attributes in fsp_param & romstage.c 6. Add required headers into include/soc/ from jasperlake directory Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If2bbe0b8a12bb78b3650f9d0a60f002f7eacb513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>