coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-07-12	soc/intel/*/pmc.c: Use newer function for resource declarations	Arthur Heymans
	Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I852d6daebdcb8461c18e7c0eaf1c54ad7c59c0c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-11-08	soc/intel: Use `PWRMBASE` over static `Index 0` for PMC	Subrata Banik
	This patch replaces static index 0 for PMC read resources with PCI configuration offset 0x10 (PWRMBASE). TEST=Able to build and boot Google, Rex to OS. Without this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 With this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-06-29	soc/intel/elkhartlake: Fix PMC read_resources callback	Tim Wawrzynczak
	The `limit` field for the PMC fixed BAR was incorrectly set to the `base + size + 1`, where it should be `base + size - 1`, to correctly tell the allocator the limit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib2d8c7ffe87fdd970f3172bb4e6b2c9386859ab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65460 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22	device/resource: Add _kb postfix for resource allocators	Kyösti Mälkki
	There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15	soc/intel/*/pmc: Add `finalize` operation for pmc	Subrata Banik
	This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs, i.e., Ready to Boot and End Of Firmware. Additionally, move the PMCON status bit clear operation to `.final` ops to cover any such chances where FSP-S Notify Phase or any other later boot stage may request a global reset and PMCON status bit remains set. BUG=b:211954778 TEST=Able to build brya with these changes. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2021-10-17	soc/intel: implement ACPI timer disabling per SoC and drop common code	Michael Niewöhner
	Since it's just a one-liner, implement disabling of the ACPI timer in soc code. This reduces complexity. Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17	soc/intel: move disabling of PM Timer to SoC PMC code	Michael Niewöhner
	Move disabling of PM Timer to SoC PMC code. The original reason for placing that in `finalize` [1] was FSP hanging due to use of the PM timer without enabling timer emulation first in coreboot, which was added later [2]. [1] commit 6c1bf27dae (intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown) [2] commit f004f66ca7 (soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs) Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-29	soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacks	Michael Niewöhner
	The current names of the PMC init/enable callbacks are very confusing. Rename them. Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-10	soc/intel/elkhartlake: Switch to runtime generation of Power Engine	Tim Wawrzynczak
	The pep.asl file is being obsoleted by runtime generation, therefore switch elkhartlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-21	soc/intel: Move pmc_soc_set_afterg3_en() to pmutil.c	Angel Pons
	Commit 2c26108208e4aa48de21be576ab6cad9286d7934 moved this function to pmutil.c for Tiger Lake. Do this to all other platforms for consistency. For Skylake, __SIMPLE_DEVICE__ preprocessor guards are no longer needed. With this change, pmc.c is only needed in ramstage. Adjust Makefile.inc accordingly, and drop ENV_RAMSTAGE guards from Skylake. Change-Id: I424eb359c898f155659d085b888410b6bb58b9ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-08	soc/intel/elkhartlake: Do initial SoC commit till ramstage	Tan, Lean Sheng
	Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Replace "jsp" with "mcc" 4. Rename structure based on Jasperlake with Elkhartlake 5. Clean up upd override in fsp_params.c will be added later 6. Sort #include files alphabetically as per comment 7. Remove doc details from espi.c until it is ready 8. Remove pch_isclk & camera clocks related codes 9. Add new #define NMI_STS_CNT & NMI_EN as per comment Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>