| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-12-14 | soc/intel/elkhartlake: Update HECI Control Status Register settings | Tan, Lean Sheng |
| 2020-09-08 | soc/intel/elkhartlake: Do initial SoC commit till ramstage | Tan, Lean Sheng |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |