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2021-10-22soc/intel/elkhartlake: Add PSE PCI devices into header fileLean Sheng Tan
Since PSE devices could be initialized as either host owned (PCI devices) or PSE owned (will be hidden from coreboot and only visible to PSE interface), add all PSE devices in PCI list header file for future usage. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Iaa40cdcb021d05e50504dd85f94e9c021e284d00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58466 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registersMichael Niewöhner
Add NMI_EN and NMI_STS registers, so NMI interrupts can be used. References: - XEON-SP: Intel doc# 633935-005 and 547817 rev1.5 - ICL-LP: Intel doc# 341081-002 - TGL-LP: Intel doc# 631120-001 - TGL-H: Intel doc# 636174-002 - JSL: Intel doc# 634545-001 - EHL: Intel doc# 636722-002 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
2021-06-10soc/intel/elkhartlake: Fix gpio_soc_defs.h variable typoLean Sheng Tan
Fix GPIO_COM2_END from GPIO_RSVD_2 to GPIO_RSVD_12. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I670f4bec8f141da73428010371754746a455df25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55334 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/intel/elkhartlake: Minor fix for SCS & XHCI devices in ACPITan, Lean Sheng
1. Remove the extra UAB devices in xhci.asl 2. Update SD controller ADR in scs.asl 3. Remove the unused SCS PID Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I1906fb4e6893dc5e2b0bc8d85f4a7b2efc85c3a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54867 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/elkhartlake: Update GPIO communitiesTan, Lean Sheng
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups in coreboot so that they are mapped properly. GPIO communities should be properly configured in GPIO_CFG and MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured in GPIO_CFG register while the PMC_GPP_* in pmc.h. GPIO communities in coreboot should match with the kernel gpio communities also. Kernel reads the ASL file from coreboot. This patch adds the proper community mapping in ASL code to match with kernel code. In gpio_soc_defs.c file we are indexing the groups correctly. In gpio.h file we define all the gpio devices as kernel populates sysfs with separate gpio device for each community. This patch is created based on Intel EHL PCH Datasheet with Document number 614109 and Chapter 21. Also update GPIO COM3 Port ID and 2 GPIO register values (HOSTSW_OWN_REG_0 & PAD_CFG_BASE) respectively. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifc609b3d6ab9ea2b807dc0f178ec99f95d2db4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-03-27soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik
Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-20soc/intel: Drop unused `GPIO_NUM_GROUPS` macroAngel Pons
This macro is unused and its value is often wrong. Drop it. Change-Id: Id3cfaa4d2eef49eddc02833efbe14e0c5c816263 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51662 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Drop `bootblock_cpu_init()` functionAngel Pons
Just call `fast_spi_cache_bios_region()` directly instead. Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Drop `romstage_pch_init()` functionAngel Pons
It only calls `smbus_common_init()`, so just call that directly. Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common smbus.hAngel Pons
Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common gpe.hAngel Pons
The definitions are identical across seven platforms. Unify them. Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16soc/intel: Drop aliases on MMCONF_BASE_ADDRESSKyösti Mälkki
Change-Id: I5ba60c1d8c314d37b4ef71c4613e6e0629da8149 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-11soc/intel/{icl,tgl,jsl,ehl}: add LPIT supportMichael Niewöhner
Add SLP_S0 residency register and enable LPIT support. Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048 Reviewed-by: Lance Zhao Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update IRQ routing settingsTan, Lean Sheng
Update IRQ routing settings. Extra reference: - ACPI spec 6.2.13 _PRT Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-14soc/intel/elkhartlake: Update USB_PORT_MID pin settingsTan, Lean Sheng
Update Pre-emphasis, Transmitter Emphasis & Preemphasis Bias values for USB_PORT_MID. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I43eeb0fc410197a559df97b340135fac65c00aa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48541 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update SerialIO devices detailsTan, Lean Sheng
Add I2C #6 & #7 and remove GSPI #3 as per EHL EDS. Also update device function number for GSPI #2 in asl file. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If166fefe567a857ca29527d0367197139efbf6c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48540 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update HECI Control Status Register settingsTan, Lean Sheng
For EHL, SpiProtectionMode is added to HFSTS register #1. The original Manufacturing Mode is detected via FpfSocConfigLock instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode, and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/48539 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update PCI device definitionTan, Lean Sheng
This change updates PCI device definition according to EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ibf7ef3c30deab5398361bc18fc63ac39fc914d8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48444 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Add EHL CRB memory initialization supportTan, Lean Sheng
Update memory parameters based on memory type supported by Elkhart Lake CRB: 1. Update spd data for EHL LPDDR4X memory - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Add configurations for vref_ca & interleaved memory 3. Add EHL CRB on board LPDDR4X SPD data bin file 4. Update mainboard related FSPM UPDs as part of memory initialization Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10soc/intel/elkhartlake: Fix EHL mainboard build fail errorsTan, Lean Sheng
When EHL initial mainboard patch is uploaded, there are some build errors caused by EHL soc codes. Here are the fixes: 1. include gpio_op.asl to resolve undefined variables in scs.asl 2. remove unused variables in fsp_params.c 3. rearrage sequences of #includes to fix build dependency of soc/gpio_defs.h in intelblocks/gpio.h 4. add the __weak to mainboard_memory_init_params function 5. add the missing _len as per this patch changes https://review.coreboot.org/c/coreboot/+/45873 Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47804 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21soc/intel: convert XTAL frequency constant to KconfigMichael Niewöhner
This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-05soc: move mainboard_get_dram_part_num prototype to memory_info.hNick Vaccaro
BUG=b:169774661, b:168724473 TEST="emerge-volteer coreboot && emerge-nocturne coreboot && emerge-dedede coreboot" and verify they build successfully. Change-Id: I8b228475621ca1035fe13f8311355fc3b926e897 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05mb, soc: change mainboard_get_dram_part_num() prototypeNick Vaccaro
Change mainboard_get_dram_part_num() to return a constant character pointer to a null-terminated C string and to take no input parameters. This also addresses the issue that different SOCs and motherboards were using different definitions for mainboard_get_dram_part_num by consolidating to a single definition. BUG=b:169774661, b:168724473 TEST="emerge-volteer coreboot && emerge-dedede coreboot && emerge-hatch coreboot" and verify build completes successfully. Change-Id: Ie7664eab65a2b9e25b7853bf68baf2525b040487 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45873 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel: Make use of PMC low power program from common blockSubrata Banik
List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function. Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel: Move pch_misc_init() to common codeSubrata Banik
List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/intel/elkhartlake: Update SA & PM related definitionsTan, Lean Sheng
1. Update SA base address & size 2. Update GBE control bit register value Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08soc/intel/elkhartlake: Update PMC related register definitionsTan, Lean Sheng
Update ABase, PMC GPIO value sets and PMC register base address. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Iba43b791cab0665ddebfbed68b7e2d15406ad206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08soc/intel/elkhartlake: Do initial SoC commit till ramstageTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Replace "jsp" with "mcc" 4. Rename structure based on Jasperlake with Elkhartlake 5. Clean up upd override in fsp_params.c will be added later 6. Sort #include files alphabetically as per comment 7. Remove doc details from espi.c until it is ready 8. Remove pch_isclk & camera clocks related codes 9. Add new #define NMI_STS_CNT & NMI_EN as per comment Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-31soc/intel/elkhartlake/romstage: Do initial SoC commit till romstageTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 4. Clean up upd override in fsp_params.c, will be added later 5. Temporarily remove _weak attributes in fsp_param & romstage.c 6. Add required headers into include/soc/ from jasperlake directory Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If2bbe0b8a12bb78b3650f9d0a60f002f7eacb513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-31soc/intel/elkhartlake/bootblock: Do initial SoC commit until bootblockTan, Lean Sheng
Clone entirely from Jasperlake This patch is based on TGL_upstream series patches: https://review.coreboot.org/c/coreboot/+/36550 List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 6. Add required headers into include/soc/ from JSL directory Elkhart Lake specific changes will follow in subsequent patches. 1. soc/intel/elkhartlake: Update Kconfig Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I9f91c1efa81a358b1f59e032e209e07b62d54613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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