coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-07-17	soc/intel/elkhartlake: Expose FIVR config to mainboard	Lean Sheng Tan
2021-06-30	soc/intel/elkhartlake: Enable PCH GBE	Lean Sheng Tan
2021-06-21	soc/intel/elkhartlake: Expose In-Band ECC config to mainboard	Werner Zeh
2021-06-11	soc/intel/elkhartlake: Update FSP-S FuSa related settings	Lean Sheng Tan
2021-06-11	soc/intel/elkhartlake: Update FSP-S PM & Thermal related configs	Lean Sheng Tan
2021-06-04	soc/intel/elkhartlake: Update FSP-S storage related configs	Lean Sheng Tan
2021-06-04	soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs	Lean Sheng Tan
2021-06-01	soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs	Tan, Lean Sheng
2021-05-30	soc/intel/elkhartlake: Update FSP-M UPD related configs	Tan, Lean Sheng
2021-04-21	soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC	Rizwan Qureshi
2021-03-03	soc/intel: Retype `CnviBtAudioOffload` devicetree option	Angel Pons
2021-01-18	soc/intel/common: Move L1_substates_control to pcie_rp.h	Eric Lai
2020-12-14	soc/intel/elkhartlake: Drop unreferenced devicetree settings	Angel Pons
2020-11-09	soc/intel/*/chip: Remove unused devicetree entry	Patrick Rudolph
2020-10-26	mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`	Michael Niewöhner
2020-09-08	soc/intel/elkhartlake: Do initial SoC commit till ramstage	Tan, Lean Sheng