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Move definitions of DMI control register and Secure Register
Lock (SRL) bit into common/block/dmi driver header file.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates bootblock_pch_early_init() to perform P2SB
configuration before any other PCH controllers are initialized. This
is done because the other controllers might perform PCR settings which
requires the PCR base address to be configured. As the PCR base
address configuration happens during P2SB initialization, this change
moves the p2sb init calls before any other PCH controller
initialization.
BUG=b:171534504
Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47885
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update ABase, PMC GPIO value sets and PMC register base address.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Iba43b791cab0665ddebfbed68b7e2d15406ad206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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1. Add CPU, SA, PCH & IGD DIDs table into report_platform.c
2. Add additional EHL SA DID in pci_ids.h
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I5c98089873b17f82560eba13c7de3353b6d3e249
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Clone entirely from Jasperlake
This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/36550
List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Rename structure based on Jasperlake with Elkhartlake
6. Add required headers into include/soc/ from JSL directory
Elkhart Lake specific changes will follow in subsequent patches.
1. soc/intel/elkhartlake: Update Kconfig
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9f91c1efa81a358b1f59e032e209e07b62d54613
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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