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2024-09-04soc/intel: Refactor ITSS macrosSubrata Banik
This patch refactors ITSS related SoC specific macros by consolidating them into a common itss.h file. This improves code maintainability and reduces redundancy as each SoC previously defined the same macros. Specific changes include: - Move SoC specific ITSS macros into intelblocks/itss.h. - SoC code now includes intelblocks/itss.h instead of the SoC-local soc/itss.h. - Drop soc/itss.h from static ASL files. - Delete soc/itss.h from all SoC locals except Apollo Lake and Sky Lake. TEST=Able to build and boot google/hatch, google/xol and google/karis. Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-11-02soc/intel/*: Correct ACPI device name for eMMCMatt DeVillier
The ACPI name of any device needs to match the name used for generating the S0i3 LPI constraint list, which comes from soc_acpi_name() for each SoC. The names used for the eMMC controller do not match, which will lead to broken ACPI tables since the LPI constriant will reference an ACPI device which does not exist. Some OSes tolerate this better than others, but it should still be corrected. TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify no invalid device names referenced. Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78825 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-07-13soc/intel: Rename pcr.asl to pch_pcr.aslSubrata Banik
The PCR (Private Configuration Register) is applicable to access the P2SB register space starting with the Intel SkyLake generation of SoC. Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in SoC die (same as PCH die for U/H SoC) and another in IOE die. This patch renames pcr.asl to pch_pcr.asl to reflect the actual source of the P2SB IP in the die (i.e., SoC die or PCH die). BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-18soc/intel/elkhartlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I73bac9560d0ff315d6fe6f4efc3ee9011f77c660 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72036 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-25soc/intel/elkhartlake: Add PSE TSN supportLean Sheng Tan
Enable PSE GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Add PSE GBE ACPI devices 3. Refactor PCH GBE FSP-S code and merge it together with PSE GBE code Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-09-10soc/intel/elkhartlake: Switch to runtime generation of Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch elkhartlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-30soc/intel/elkhartlake: Enable PCH GBELean Sheng Tan
Enable PCH GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Use EHL own GBE ACPI instead of common code version due to different B:D.F from the usual GBE 3. Add kconfig PMC_EPOC to use the PMC XTAL read function Due to EHL GBE comes with time sensitive networking (TSN) capability integrated, EHL FSP is using 'PchTsn' instead of the usual 'PchLan' naming convention across the board. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-26soc/intel/elkhartlake: Minor fix for SCS & XHCI devices in ACPITan, Lean Sheng
1. Remove the extra UAB devices in xhci.asl 2. Update SD controller ADR in scs.asl 3. Remove the unused SCS PID Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I1906fb4e6893dc5e2b0bc8d85f4a7b2efc85c3a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54867 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/elkhartlake: Update GPIO communitiesTan, Lean Sheng
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups in coreboot so that they are mapped properly. GPIO communities should be properly configured in GPIO_CFG and MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured in GPIO_CFG register while the PMC_GPP_* in pmc.h. GPIO communities in coreboot should match with the kernel gpio communities also. Kernel reads the ASL file from coreboot. This patch adds the proper community mapping in ASL code to match with kernel code. In gpio_soc_defs.c file we are indexing the groups correctly. In gpio.h file we define all the gpio devices as kernel populates sysfs with separate gpio device for each community. This patch is created based on Intel EHL PCH Datasheet with Document number 614109 and Chapter 21. Also update GPIO COM3 Port ID and 2 GPIO register values (HOSTSW_OWN_REG_0 & PAD_CFG_BASE) respectively. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifc609b3d6ab9ea2b807dc0f178ec99f95d2db4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-03-01soc/intel: Include gfx.asl from northbridgeAngel Pons
The iGPU is on the northbridge or system agent, not the southbridge. Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30soc/intel/common: Move gfx.asl to drivers/intel/gmaMatt DeVillier
Adjust platform-level includes as needed. Change-Id: I376349ccddb95c166f0836ec1273bb8252c7c155 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14soc/intel/elkhartlake: Update IRQ routing settingsTan, Lean Sheng
Update IRQ routing settings. Extra reference: - ACPI spec 6.2.13 _PRT Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-14soc/intel/elkhartlake: Update USB & PCIe devices in ASL filesTan, Lean Sheng
Update USB & PCIe devices in ASL files as per EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-14soc/intel/elkhartlake: Update SerialIO devices detailsTan, Lean Sheng
Add I2C #6 & #7 and remove GSPI #3 as per EHL EDS. Also update device function number for GSPI #2 in asl file. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If166fefe567a857ca29527d0367197139efbf6c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48540 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/intel/elkhartlake: Fix EHL mainboard build fail errorsTan, Lean Sheng
When EHL initial mainboard patch is uploaded, there are some build errors caused by EHL soc codes. Here are the fixes: 1. include gpio_op.asl to resolve undefined variables in scs.asl 2. remove unused variables in fsp_params.c 3. rearrage sequences of #includes to fix build dependency of soc/gpio_defs.h in intelblocks/gpio.h 4. add the __weak to mainboard_memory_init_params function 5. add the missing _len as per this patch changes https://review.coreboot.org/c/coreboot/+/45873 Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47804 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPDMichael Niewöhner
Replace the two obsolete LPID implementations with the new PEPD device. The PEPD device gets included in the plaforms' `southbridge.asl`, since it is required to load the `intel_pmc_core` module in Linux, which checks for the _HID. (See CB:46469 for more info on that.) There is no harm for mainboards not supporting S0ix, because the _DSM function won't be called with the LPS0 UUID on such boards. Such boards can use the debugging functionality of `intel_pmc_core`, too. Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/intel: Make use of common gfx.aslSubrata Banik
Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI devices and methods. TEST=Able to build and boot TGL platform Dump and disassemble DSDT, verify GFX0 device present as below Device (GFX0) { Name (_ADR, 0x00020000) // _ADR: Address } Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common smbus.aslSubrata Banik
This patch moves smbus.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify SBUS device present inside common smbus.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib1ae48f7ece3e521501d92c40cd551287ea2f1ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/45979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common pch_glan.aslSubrata Banik
This patch moves pch_glan.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify GLAN device present inside common pch_glan.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/45975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlakeTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Rename from jasperlake to elkhartlake 2. Remove irelevant devices asls (ipu,ish,camera clock,gpio_op) Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I5e77081d1673cc0ca97edc63e9996c045ab6e9b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44812 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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