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2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17Reland "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit acbc4912375085a099c2427def464d6e481f2a90. Reason for revert: CB:79525 fixes the issue that led to the revert by not maintaining the heap in the SMM-stored copy of ramstage at all. Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07Revert "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6. Reason for revert: It breaks wakeup from suspend on a bunch of boards. While this approach of eyeballing "correct" values by chipset _should_ be fixed, it should also be accompanied by compile time verification that the memory map works out. Since nobody seems to care enough, let's just revert this, instead of keeping the tree broken for a bunch of configurations. Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-11Kconfig: Bring HEAP_SIZE to a common, large valuePatrick Georgi
We have a tiny HEAP_SIZE by default, except when we don't, and mainboards that override it, or not. Since memory isn't exactly at a premium these days, and unused heap doesn't cost anything extra, just crank it up to the highest value we have in the tree by default and remove all overrides. Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21soc: Remove SOC_SPECIFIC_OPTIONSElyes Haouas
Move specific options under the boolean and remove dummy SOC_SPECIFIC_OPTIONS. Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-23soc/intel/elkhartlake: Define DIMM_SPD_SIZE in SoC KconfigMichał Żygowski
The default SPD size is set to 256 bytes, instead of 512 for LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused the SMBus libraries to read only the lower half of the DIMM SPD on protectli/vault_ehl. The lower half of the SPD passed to FSP causes a bug in DIMM change detection, which relies on the CRC of the manufacturer bytes in the upper half of the SPD (CRC of zero bytes always gives zero so no change was assumed). Setting the DIMM SPD size to 512 fixes it. Setting the SPD size in SoC will also avoid such problems in the future Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing the correct default of 512 bytes is an obvious thing to do. TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see FSP is retraining the memory instead of doing the fastboot with old DIMM data. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-22soc/intel/elkhartlake: Increase BSP stack size by 1 KiB to 193 KiBMichał Żygowski
The Kconfig help section says FSP uses 192 KiB of stack (0x30000) and coreboot's romstage requires ~1 KiB, but it is not satisfied currently. Increase the BSP stack size by the missing 1KiB for romstage like other SoCs do. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iddd4a4613bc174aec4331732371a27450225258c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73820 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-15soc/intel/elkhartlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8f8a0bfeaea508d3b4ad1b3fe2e68742cbab5570 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73687 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/ehl: Select CSE defined ME spec version for elkhartlakeDinesh Gehlot
Elkhartlake based SoCs uses Intel's Management Engine (ME), version 15. This patch selects ME 15 specification defined at common code and removes elkhartlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I3186f509c63b3a892c72cb1fa08fc094735d6eeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73245 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-11-09soc/intel/elkhartlake: Correct I2C base clock to 100 MHzWerner Zeh
According to measurements Elkhart Lake seems to drive the internal I2C controllers with 100 MHz instead of the common 133 MHz. The datasheet itself is quite vague on this definition, just one place mentions that it is 100 MHz (register description for offset 0x94). This patch changes the I2C controller base frequency to 100 MHz. The verification was done by measuring the set up resulting I2C clock for both 100 and 400 kHz. Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-10-22payloads/edk2: Disable the CPU Timer Lib unless supportedSean Rhodes
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp Counter Frequence. For CPUs that do not support this instruction, EDK2 must include a different library which is the reason why this must be configured at build time. If this is enabled, and the CPU doesn't support 0x15, it will fail to boot. If is not enabled, and the CPU does support 0x15, it will still boot but without support for the leaf. Consequently, disabled it by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-12soc/intel: Kconfig: Correct UART source clock value in commentWonkyu Kim
Correct UART source clock value in comment from 120 MHz to 100 MHz. BUG=b:249530903 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc17357051ae0b3bc663da467b4fc809a46024d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68286 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20soc/intel/common/pch: Decouple CLIENT from BASEAngel Pons
In preparation to add a third option, have "Client" platforms select a dedicated Kconfig option instead of the common "_BASE" option. Rewrite the help texts to clarify what "Client" and "Server" mean, because the terms refer to the type of silicon and not to the market segment. Some uniprocessor (single-socket) servers are actually client platforms and there are some multi-socket workstations based on a server platform. Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-05soc/intel/elkhartlake: Remove board related vboot kconfigs from socLean Sheng Tan
Since the non-volatile storage as it handles VBNV storage in either flash or CMOS, is chosen based on board design, removing VBOOT_VBNV_CMOS & VBOOT_VBNV_CMOS_BACKUP_TO_FLASH from EHL soc kconfig. Will add the option to EHL CRB mainboard kconfig later. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I97fb7017bff7751d64571d1a8ee7c8b9e2771731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64473 Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-03soc/intel/elkhartlake: Select SOC_INTEL_RAPL_DISABLE_VIA_MCHBARUwe Poeche
Since of moving RAPL disabling to common code a config switch is available to select that RAPL disabling has to be done via MCHBAR. This patch selects the switch for EHL. Test: Boot mc_ehl1 and ensure that relevant bits in MCHBAR are the same as before the patch. Change-Id: I1d0b7f650aa3ccf89c5c35d9b60a83a1ce48c74f Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-18soc/intel/elkhartlake: Skip FSP Notify APIsLean Sheng Tan
Follow this commit 95986169f (soc/intel/alderlake: Skip FSP Notify APIs) to skip FSP Notify APIs. Elkhart Lake SoC deselects Kconfigs as below: - USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE to skip FSP notify APIs (Ready to boot and End of Firmware) and make use of native coreboot driver to perform SoC recommended operations prior booting to payload/OS. When deselecting these Kconfigs, cse_final_ready_to_boot() and cse_final_end_of_firmware() in the common cse driver will be used instead as required operations to perform prior to booting to OS. Check out this CL for further info: commit 90e318bba (soc/intel/common/cse: Add `finalize` operation for CSE) Additionally, create a helper function `heci_finalize()` to keep HECI related operations separated for easy guarding again config. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I477c204233f83bc96fd5cd39346bff15ed942dc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16soc/intel/elkhartlake: Implement TSN GbE driverMario Scheithauer
To be able to make EHL Ethernet GbE-TSN Controller configurable, a driver is required. Functionality comes in following patches. Change-Id: I7522914c56b74486bb088280d2686acf7027d1d3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-29soc/{amd/stoneyridge,intel}: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans
Now the bootblock is not limited to 64K so integrating vboot into the bootblock reduces the binary size. intel/apl is an exception since the bootblock size is limited to 32K. Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-29soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik
This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-18drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-02soc/intel/elkhartlake: Use SBI msg to disable HECI1Subrata Banik
Select HECI_DISABLE_USING_SMM config for Elkhart Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4ef7ff7aa234ce411092d70bcb2c9141609be90e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-01-30soc/intel/elkhartlake: Drop stale eNEM TODO commentSubrata Banik
This patch drops stale TODO comment about enabling eNEM on EHL. eNEM is non-POR on the elkhartlake product. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-25soc/intel/ehl: Add Kconfig option to disable reset on TCO expirationWerner Zeh
The TCO timer is the default watchdog of an x86 host and can reset the system once it has expired for the second time. There are applications where this reset is not acceptable while the TCO is used. In these applications the TCO expire event generates an interrupt and software takes care. There is a bit in the TCO1_CNT register on Elkhart Lake to prevent this reset on expiration (called NO_REBOOT, see doc #636722 ). This bit can either be strapped on hardware or set in this register to avoid the reset on expiration. While the hardware strap cannot be overridden in software, the pure software solution is more flexible. Unfortunately, the location for this bit differs among the different platforms. This is why it has to be handled on soc level rather than on TCO common code level. This commit adds a Kconfig option where NO_REBOOT can be enabled. This makes it easy to reach this feature over to the mainboard where it can be selected if needed. Change-Id: Iaa81bfbe688edd717aa02db86f0a93fecdfcd16b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-25soc/intel/elkhartlake: Introduce Intel PSELean Sheng Tan
The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and its peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate the PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate the PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enable the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-01-09soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entriesMichael Niewöhner
Enable CPPC entries generation, needed for Intel SpeedShift. This can be tested by checking sysfs in Linux: $ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf The output should look like this, while the values may differ: /sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1 /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24 /sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5 ... Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2021-12-12soc/intel/elkhartlake: Hook up public microcodeArthur Heymans
Change-Id: I1d975713129d0a7bce823232d225ed17ee28a04d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-08soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`Michael Niewöhner
Technically, it's not depending on the hardware but on the software (OS/payload), if the PM Timer is optional. OSes with ACPI >= 5.0A support disabling of the PM Timer, when the respective FADT flag is unset. Thus, drop this guard. For platforms without hardware PM Timer (Apollo Lake, Gemini Lake) the Kconfig `USE_PM_ACPI_TIMER` depends on `!NO_PM_ACPI_TIMER`. As of this change, new platforms must either implement code for disabling the hardware PM timer or select `NO_PM_ACPI_TIMER` if no such is present. Change-Id: I973ad418ba43cbd80b023abf94d3548edc53a561 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao
2021-10-22arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki
For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-17soc/intel: implement ACPI timer disabling per SoC and drop common codeMichael Niewöhner
Since it's just a one-liner, implement disabling of the ACPI timer in soc code. This reduces complexity. Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-12soc/intel: replace dt option PmTimerDisabled by KconfigMichael Niewöhner
Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-29soc/intel: Drop unnecessary `select REG_SCRIPT`Angel Pons
These platforms no longer use reg-script. Drop unneeded select. Change-Id: I8fc4dc29d25dffbf9ed1947d0ff013b2fae0faaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-10soc/intel/elkhartlake: Switch to runtime generation of Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch elkhartlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-29soc/intel/elkhartlake: Update UART clock divider paramsLean Sheng Tan
As EHL UART source clock is 120MHz, update the clock divider parameters (M & N) to reflect the right value. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I30c21bc4d1ef901a318a12664b61be75c1acf23b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-19soc/intel/common: Rename kconfig PMC_EPOCLean Sheng Tan
Rename PMC_EPOC to SOC_INTEL_COMMON_BLOCK_PMC_EPOC to maintain common naming convention. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If8a264007bbb85a44bbdfa72115eb687c32ec36e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-02src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-30soc/intel/elkhartlake: Enable PCH GBELean Sheng Tan
Enable PCH GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Use EHL own GBE ACPI instead of common code version due to different B:D.F from the usual GBE 3. Add kconfig PMC_EPOC to use the PMC XTAL read function Due to EHL GBE comes with time sensitive networking (TSN) capability integrated, EHL FSP is using 'PchTsn' instead of the usual 'PchLan' naming convention across the board. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-30src: Move `select ARCH_X86` to platformsAngel Pons
To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware, have platforms select `ARCH_X86` directly instead of through per-stage Kconfig options, effectively reversing the dependency order. Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-10soc/intel/elkhartlake: Use FSP from FSP repo by defaultLean Sheng Tan
Select 'HAVE_INTEL_FSP_REPO' so that the FSP binary from the FSP repository is used by default. Also, use the FSP headers from the FSP repository instead. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I0c1bcb07ed0f73e1d5ada5f6f16b84816c4ef3d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55229 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-04soc/intel/elkhartlake: Update FSP-S storage related configsLean Sheng Tan
Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-04-21soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRCRizwan Qureshi
CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config is for the number of PCIe Clock sources available which is different from PCIe clock reqs. This is more relevant in alderlake, as the number clock source and clock reqs differ. However since this is a better name, renaming it throughout the soc/intel tree. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel: Factor out common smmrelocate.cAngel Pons
There are seven identical copies of the same file. One is enough. Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out identical acpigen GPIO helpersAngel Pons
Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
Always allocate RAMOOPS from CBMEM and drop the related static variable CHROMEOS_RAMOOPS_RAM_START. Change-Id: Icfcf2991cb78cc6e9becba14cac77a04d8ada56a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50608 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06drivers/intel/fsp2_0: Add support for MP services2 PPIAamir Bohra
Add support for MP services2 PPIs, which is slight modification over MP services 1 PPIs. A new API StartupAllCPUs have been added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES parameter has been removed from all MP PPI APIs. This implementation also selects the respective MP services PPI version supported for SoCs BUG=b:169196864 Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-06intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh
This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI in preparation to allow V1 and V2 versions of MP services PPI. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06intel: Drop FSP_PEIM_TO_PEIM_INTERFACEFurquan Shaikh
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE. FSP_PEIM_TO_PEIM_INTERFACE is used for: * Auto-selecting FSP_USES_MP_SERVICES_PPI * Including src/drivers/intel/fsp2_0/ppi/Kconfig * Adding ppi to subdirs-y * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y and is selected by SoCs that want to enable MP PPI services. Instead of using the indirect path of selecting MP PPI services, this change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The above uses are handled as follows: * Auto-selecting FSP_USES_MP_SERVICES_PPI --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI. * Including src/drivers/intel/fsp2_0/ppi/Kconfig --> The guard isn't really required. The Kconfig options in this file don't present user prompts and don't really need to be guarded. * Adding ppi to subdirs-y --> Makefile under ppi/ already has conditional inclusion of files and does not require a top-level conditional. * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01src/soc/intel: Remove CPU_INTEL_COMMON_SMM selectionElyes HAOUAS
CPU_INTEL_COMMON_SMM is already selected in cpu/intel/common/Kconfig file. Also remove duplicated 'CPU_INTEL_COMMON'. Change-Id: I3328da567ac588e9bf6d57481fca117cc302a23a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once. Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki
With top-aligned bootblock this is no longer globally needed. The default maximum is now a generous 256 KiB with couple platforms having lower limits of 32 KiB and 64 KiB. Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-11soc/intel/{icl,tgl,jsl,ehl}: add LPIT supportMichael Niewöhner
Add SLP_S0 residency register and enable LPIT support. Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048 Reviewed-by: Lance Zhao Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02soc/intel/elkhartlake: Update KconfigTan, Lean Sheng
Update Kconfig: 1. use FSP2.1 instead of 2.2 2. remove HECI_DISABLE_USING_SMM config 3. update CAR related stack & ram size 4. update FSP heap size 5. set IED region size = 0 as it is not used 6. update SMM TSEG size 7. update RP & I2C max device #s 8. update UART base address Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45078 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical orderSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I7adf430e6ce5f78f68a0c73af841fbdc62bb5dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47057 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02soc/intel: Use of common reset code blockSubrata Banik
This patch removes all redundant reset code block from each SoC and make use of common reset code block(fsp_reset.c) based on SOC_INTEL_COMMON_FSP_RESET. Respective SoC Kconfig to choose correct FSP global reset type as per FSP integration guide. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21soc/intel: convert XTAL frequency constant to KconfigMichael Niewöhner
This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21soc/intel/common: add Kconfig for PM Timer emulation supportMichael Niewöhner
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and select it by the appropriate SoCs. This Kconfig gets used in the follow-up changes. Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-03soc/intel: Make use of PMC low power program from common blockSubrata Banik
List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function. Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-26arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons
Nearly every x86 platform uses the same arch for all stages. The only exception is Picasso. So, factor out redundant symbols from the rest. Alder Lake is not yet complete, so it has been skipped for now. Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08soc/intel/elkhartlake: Do initial SoC commit till ramstageTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Replace "jsp" with "mcc" 4. Rename structure based on Jasperlake with Elkhartlake 5. Clean up upd override in fsp_params.c will be added later 6. Sort #include files alphabetically as per comment 7. Remove doc details from espi.c until it is ready 8. Remove pch_isclk & camera clocks related codes 9. Add new #define NMI_STS_CNT & NMI_EN as per comment Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-25 14:17:37 +0000