coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-01-24	Revert "soc/intel/denverton_ns: Rewrite pmutil using pmclib"	Patrick Georgi
	This reverts commit ab1227226ebd78b40783cb200e60711b900352f0. There were significant changes around soc_reset_tco_status() that this code needs to be adapted to. Change-Id: I563c9ddb3c7931c2b02f5c97a3be5e44fa873889 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24	soc/intel/denverton_ns: Rewrite pmutil using pmclib	Julien Viard de Galbert
	Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25427 Reviewed-by: David Guckian Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03	soc/intel: Fix bad uses of __SIMPLE_DEVICE__	Kyösti Mälkki
	Cases of *dev = PCI_DEV(b,d,f) are invalid. Not caught because files only build with __SIMPLE_DEVICE__ defined. Remove cases of testing __SIMPLE_DEVICE__ in files that are not build for ramstage. Change-Id: If10a0efa187c9b1d9a5577008aa46f050f0aa309 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-14	src: Get rid of device_t	Elyes HAOUAS
	Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-05	soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC	Mariusz Szafranski
	This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>