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2024-05-06common/block/tcss: Add config for PDC<->PMC mux configurationKrishna Prasad Bhat
Introduce a new Kconfig to enable PD controller to PMC mux configuration. Selecting this config enables direct communication from PDC to PMC. TCSS_HAS_USBC_OPS enables USB-C operations via the EC. When SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION is selected, disable TCSS_HAS_USBC_OPS to avoid sending PMC commands from AP/EC. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: Ieeb503393418cdad43384be39ac49c93ba91e4db Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82077 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06block/fast_spi: Use read32p/write32p for SPI RWAshish Kumar Mishra
The current fast_spi code uses memcpy for rw. The SPI flash read/write has 4 byte limit, due to which the current 64 bit memcpy doesn't work. Hence update rw ops to use read32p/write32p. BUG=b:242829490 TEST=Verified MRC cache working on MTL 64-bit, future 64 bit platforms and RPL(brox/skolas) 32-bit platforms. Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-29soc/intel/cmn/graphics: Make DDI-A 4 lanes configurableAngel Pons
As described in Intel document 336464 (8th gen S series datasheet volume 1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2 lanes. This lets mainboards provide a VGA output without sacrificing one of the main 4-lane DDIs. Newer platforms seem to be lacking this. However, the way this is structured in coreboot does not allow boards to choose whether bifurcation should be enabled. Most boards in the tree do not use DDI-E (it doesn't exist on mobile platforms), but there are some boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to provide a VGA output. Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to specify whether a platform supports DDI-A bifurcation at all (do nothing otherwise, maintaining the original code's behaviour). If bifurcation is supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register. Change-Id: I516538db77509209d371f3f49c920476e06b052f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DIDMichał Kopeć
Found in a Clevo V560TU with Intel Core Ultra 155H Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82071 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-23soc/intel/alderlake: Add Twinlake graphics device IDsSowmya V
Add the graphics device IDs for Twinlake platform based on Platform External Design Specification. Document ID: 645548 BUG=b:326901448 TEST=Build tivviks and verify the IGD IDs. Change-Id: Ide008d5c5302bd589784bc917a2610c42a0fdee4 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82038 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-22drivers/intel/fsp2_0: Introduce fsp print helper macrosAppukuttan V K
This patch introduces fsp print helper macros to print `efi_return_status_t' with the appropriate format. These macros are now used for fsp debug prints with return status efi_return_status_t is defined as UINT64 or UNIT32 based on the selected architecture BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: If6342c4d40c76b702351070e424797c21138a4a9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81630 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12tree: Drop unused <cbmem.h>Elyes Haouas
Change-Id: If8be8dc26f2729f55dc6716e6d01e2b801d79e44 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-11soc/intel/**/fast_spi.c: Reorganize some statementsAngel Pons
Avoid calling `acpi_device_scope()` and `fast_spi_acpi_hid()` if the result won't be used. Also, reorder a condition so that compile-time constants appear first, so as to help the compiler optimize it out. Change-Id: I42ce55c2978ad9c593c359c5decd5842fb3a97a1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-10tree: Drop unused <elog.h>Elyes Haouas
Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04soc/intel/common/block/fast_spi: probe for 2nd flash componentMichał Żygowski
Fast SPI code assumes only one SPI flash is present. The SPI flash driver for older southbridges is able to detect multichip. See the spi_is_multichip() in src/southbridge/intel/common/spi.c. Some boards (e.g. Lenovo ThinkCentre M920 Tiny) still come with two chips populated instead of one. With this change, both chips are probed, and the correct total size is calculated. Otherwise, only the first one was probed, which resulted in an error such as: SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x1800000!! Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-04soc/intel/cache_as_ram_fsp.S: Drop unused preprocessing directivesArthur Heymans
Change-Id: I42bb15b8534d16401cd06ff803a8425221c5f3c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-04drivers/intel/fsp2_0: Support FSP-T in long modeArthur Heymans
Call into FSP-T using the protected mode wrapper and enter long mode in FSP-T support assembly code. TEST: Booted on ibm/sbp1 in long mode. Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-01intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASEShuo Liu
IBL (Integrated Boot Logic) provides a subset of server PCH logics for no-PCH solution. IBL is with limited features and registers exposed, PCIe root ports/USB/SATA/LAN support are removed. Change-Id: I8f3d64a2dd3b79ec5a9e4306f40b012b00387259 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81314 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30soc/intel: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-28cpu/x86: Link page tables in stage if possibleArthur Heymans
When switching back and forth between 32 to 64 bit mode, for example to call a 32-bits FSP or to call the payload, new page tables in the respective stage will be linked. The advantages of this approach are: - No need to determine a good place for page tables in CBFS that does not overlap. - Works with non memory mapped flash (however all coreboot targets currently do support this) - If later stages can use their own page tables which fits better with the vboot RO/RW flow A disadvantage is that it increases the stage size. This could be improved upon by using 1G pages and generating the pages at runtime. Note: qemu cannot have the page tables in the RO boot medium and needs to relocate them at runtime. This is why keeping the existing code with page tables in CBFS is done for now. TEST: Booted to payload on google/vilbox and qemu/q35 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-24soc/intel/common/block/cse: Remove return statement in void functionElyes Haouas
Return statement is not useful in void function. Change-Id: Idb8e07f48043452b329d255fe457f00317c017ae Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81429 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17soc/intel/cmn/ramtop: Refactor MTRR handling for RAMTOP rangeSubrata Banik
This patch refactors RAMTOP MTRR type selection to address a critical NEM logic bug on SoCs with non-power-of-two cache sets. This bug can cause runtime hangs when Write Back (WB) caching is enabled. Workaround: Force MTRR type to WC (Write Combining) on affected SoCs when the cache set count is not a power of two. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis and google/rex (including Ovis with non-power-of-two cache configuration). Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14intelblocks/pmc: Assign initial values to pmc_gpe_init variablesGang Chen
pmc_gpe_init uses soc_get_gpi_gpe_configs to initialize dw0, dw1 and dw2. dw0, dw1 and dw2 are uninitialized before calling soc_get_gpi_gpe_configs. This is error prone for some soc implementations where soc_get_gpi_gpe_configs does nothing. This patch is simple, just to assign zero values to dw0, dw1 and dw0, to enhance the code robustness. TEST=intel/archercity CRB Signed-off-by: Gang Chen <gang.c.chen@intel.com> Change-Id: I8a710a2ac1482eed8c11977d51b187d834122d26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81210 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-12soc/intel/common/block: Add support for watchdogMarek Maslanka
Implement watchdog for intel based platform by filling ACPI Watchdog Action Table (WDAT) table. The WDAT ACPI table encompasses essential watchdog functions, including: - Setting and retrieving countdown/timeout values - Starting and stopping the watchdog - Pinging the watchdog - Retrieving the cause of the last reboot, whether it was triggered by the watchdog or another reason The general purpose register TCO_MESSAGE1 stores the reason for the most recent reboot rather than the original register TCO2_STS. This is because the firmware must clear TCO2_STS, and it can't be reused for storing this information for the operating system. The watchdog is designed for use by the OS through certain defined actions in the WDAT table. It relies on the ACPI Power Management Timer, which may result in an increase in power consumption. BUG=b:314260167 TEST=Enable CONFIG_ACPI_WDAT_WDT and CONFIG_USE_PM_ACPI_TIMER in the config. Enable CONFIG_WDAT_WDT in the kernel config. Build and deploy both firmware and kernel to the device. Trigger the watchdog by performing the command: “cat > /dev/watchdog”. Wait approximately 30 seconds for the watchdog to reset the device. Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-caseJeremy Compostella
Commit 829e8e65b939 ("soc/intel: Use common codeflow for MP init") brokes `USE_INTEL_FSP_MP_INIT' by making `init_cpus' function static. This function needs to be accessible from src/drivers/intel/fsp2_0/fsp_mpinit.c. TEST=Verified on Meteor Lake rex board Change-Id: Idb8cdfef7b4279da2c7dff344c95fe446a605934 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09soc/intel/alderlake: Add Raptor Lake System Agent Device IDsLean Sheng Tan
Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet (Doc ID: 743844) & EDS Vol 1 (Doc ID: 640555). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/81115 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05soc/intel: Add definition of D0 stepping for TigerLake HaloAlicja Michalska
Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSIONSubrata Banik
This patch marks CONFIG_SOC_INTEL_CSE_RW_VERSION as deprecated, as future platforms will automatically determine the CSE RW version using CSE RW partition. BUG=b:327842062 TEST=CSE RW update successful on Screebo. Change-Id: I8c3e5c759e4d9a43c3bce3a0c032086f17592a67 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80924 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2024-03-04soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entrySubrata Banik
This patch automates the process of determining the CSE RW version used for the CBFS entry, eliminating the need for manual configuration in CONFIG_SOC_INTEL_CSE_RW_VERSION. How to get CSE RW Version: 1. Open CSE RW file as per CONFIG_SOC_INTEL_CSE_RW_FILE 2. Read offset 16 (0x10) to know the CSE version 3. Format: - CSE_VERSION_MAJOR : offset 16-17 - CSE_VERSION_MINOR : offset 18-19 - CSE_VERSION_HOTFIX: offset 20-21 - CSE_VERSION_HOTFIX: offset 22-23 Benefits: - Removes error-prone manual version updates. - Prevents boot loops due to mismatched CSE RW versions (actual vs config) - Eliminates the need for SKU-specific CSE version limitations. BUG=b:327842062 TEST=CSE RW update successful on Screebo with this patch. Example Debug Output: [DEBUG] cse_lite: RO version = 18.0.5.2066 [DEBUG] cse_lite: RW version = 18.0.5.2107 Change-Id: I0165d81b0e4b38e0e097956f250bb7484d774145 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80923 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27soc/intel/common/lpc: Don't open a window for unassigned resourcesMatt DeVillier
Don't attempt to open a PMIO window for a resource which doesn't have the IORESOURCE_ASSIGNED flag set, since there is no point in doing so and there's a high likelihood that the base address is 0, which will throw an error. TEST=build/boot purism/librem_cnl (Mini v2), ensure no errors in cbmem log for attempting to open a PMIO window for unaassigned resources with base address 0. Change-Id: Ifba14a8f134ba12d5f5e9fdbac775d4f82b4c4de Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-23arch/x86/ioapic: use uintptr_t for IOAPIC base addressFelix Held
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC- related functions to avoid needing type casts in the callers. This also allows dropping the VIO_APIC_VADDR define and consistently use the IO_APIC_ADDR define instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I912943e923ff092708e90138caa5e1daf269a69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-02-22soc/intel/common/lpc: Skip setting resources for disabled devicesMatt DeVillier
If a downstream LPC device (eg, SIO function) is disabled, we shouldn't attempt to open PMIO windows for it, as those functions often have unset IO bases (which default to 0), resulting in false errors like: [ERROR] LPC IO decode base 0! TEST=build/boot purism/librem_cnl (Mini v2), verify no LPC IO errors in cbmem log for disabled SIO functions. Change-Id: I92c79fc01be21466976f3056242f6d1824878eab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-19soc/intel/common: Add ADL_N ID 5 0x4618Sean Rhodes
This patch adds ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/80487 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18soc/intel/common/block/dtt: Add ACPI stub for TCPU deviceMatt DeVillier
Add an ACPI stub containing the TCPU device in proper scope, along with the device status, on boards not using the DPTF driver, so that there exists an ACPI device to be referenced from the PEPD LPI constraint list. Adding the stub fixes an AE_NOT_FOUND ACPI error under Linux for _SB.PCI0.TCPU on boards with the SA thermal device enabled but which do not use the Intel DPTF driver. TEST=build/boot Linux,Win11 on purism/librem_cnl (Librem Mini v2). Change-Id: I926d0461e5e0dfaf606102575c2be555a6bfb695 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-18soc/intel/common/block/sata: Fix scope for SATA ACPI deviceMatt DeVillier
acpi_device_path() includes the device name, so we end up with: Scope (\_SB.PCI0.SATA) { Device (SATA) { ... Fix this by using acpi_device_scope() instead. TEST=build/boot purism librem_cml (Mini v2), dump ACPI and verify SATA device scope correct. Change-Id: Ibbc8890d93b22f0ecba4b3a9b0531994574b3d55 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80554 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-17intelblocks/systemagent: Add missing N6005 Jasper Lake SKU to PCI ID listMichał Żygowski
Change-Id: I3fb4c6cfe24290c34682ff1c3396540465048727 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-15soc/intel/common/tcss: Rename tcss_mux_init to disconnect_tcss_devicesSean Rhodes
Rename tcss_mux_init to disconnect_tcss_devices to make it clear what this function is doing, as it doesn't initialise anything. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5e43f0cca9d49bc30fc189663490a306efd71584 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79874 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-13soc/intel/cmn/sa: Add APIs into System Agent (SA) common codeSubrata Banik
This commit streamlines code and strengthens common code robustness by moving the following SoC-layer functions to the common layer: - sa_get_mmcfg_size: Retrieves the MMIO (Memory-Mapped I/O) configuration space size by reading offset 0x60 of the PCI Host Bridge (D0:F0). - sa_get_dsm_size: Calculates the size of the DSM (Device Stolen Memory) by reading offset 0x50 of the PCI Host Bridge (D0:F0) to determine pre-allocated memory for the IGD (Integrated Graphics Device). - sa_get_gsm_size: Calculates the size of the GSM (Graphics Stolen Memory) by reading offset 0x52 of the PCI Host Bridge (D0:F0). - sa_get_dpr_size: Determines the size of the DMA Protection Range (DPR) by reading offset 0x5C of the PCI Host Bridge (D0:F0). TEST= Build and boot successful on google/screebo. Change-Id: Ic00e001563ec6f0d737a445964c716b45db43327 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-12soc/intel/cmn/sa: Refactor SA common codeSubrata Banik
Leverages common SA header definitions for Host Bridge registers. Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity. Additionally, made some minor code alignment corrections while adding newer macros in the header file. TEST= Build and boot successful on google/screebo. Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-02-08cpu/x86/64bit: Turn jumping to long mode into a macroArthur Heymans
This makes it easier to reuse, e.g. if you want to do it twice in one assembly file. Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-02-08mb/google/brox: Handle GPI_INT pin lower to GPI_WAKEAshish Kumar Mishra
In case where PAD_CFG_GPI_INT() is initialized with a pin value lower to PAD_CFG_GPI_IRQ_WAKE() for same GPIO community the set_ioapic_used() is only called for the PAD_CFG_GPI_IRQ_WAKE() pin. Due to this the IRQ associated with PAD_CFG_GPI_INT() is found free by find_free_unique_irq() during IRQ assignment and assigned to other pins which causes IRQ conflicts BUG=b:322984217 BRANCH=None TEST=Boot test on brox, check if correct IRQ assigned to EC Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80334 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-05soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPSSean Rhodes
Currently, SOC_INTEL_COMMON_BLOCK_TCSS will set MUX to disabled. The two related options to re-configure it for either USB devices or displays, are currently only supported by the ChromeEC. As such, any device without the ChromeEC will boot with attached USB-C devices in a non-functional state. Add TCSS_HAS_USBC_OPS to make this feature configurable, and set the default to enabled if the board features the ChromeEC. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79882 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-02-02lib: Move IP checksum to commonlibJulius Werner
This patch moves the IP checksum algorithm into commonlib to prepare for it being shared with libpayload. The current implementation is ancient and pretty hard to read (and does some unnecessary questionable things like the type-punning stuff which leads to suboptimal code generation), so this reimplements it from scratch (that also helps with the licensing). This algorithm is prepared to take in a pre-calculated "wide" checksum in a machine-register-sized data type which is then narrowed down to 16 bits (see RFC 1071 for why that's valid). This isn't used yet (and the code will get optimized out), but will be used later in this patch series for architecture-specific optimization. Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-30soc/intel: Unify the definition of TCO registersMarek Maslanka
Move the definition of the TCO registers used in most boards to a separate file and use it consistently. Do not unify TCO for older incompatible platforms. BUG=b:314260167 TEST=none Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-29device/device.h: Drop multiple linksArthur Heymans
Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Reviewed-on: https://review.coreboot.org/c/coreboot/+/78328 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-26soc/intel/common: Add lunarlake device IDsAppukuttan V K
Added Lunar Lake device IDs the device specific functions Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2024-01-26soc/intel/common/block/sata: Add ACPI stub for SATA deviceMatt DeVillier
Add an ACPI stub containing the SATA device in proper scope, along with the device status, so that there exists a device to be referenced from the PEPD LPI constraint list. Fixes a Windows BSOD INTERNAL_POWER_ERROR on devices with enabled SATA ports. TEST=build/boot Win11 on google/puff (kaisa). Change-Id: I951c62d09609ed73079fe97ea9ce49fdee333272 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24soc/intel: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-22soc/intel/cmn/block/pmc: Fix prev_sleep_state string name mappingAnil Kumar
commit d078ef2152052b5ce8686249dcd05ebd50010889 ("soc/intel/cmn/block/pmc: Add previous sleep state strings in log") used SLP_TYP numbers to map ACPI sleep state value. This incorrectly printed wrong string for prev_sleep_state during S5. ex: after a cold reset the previous sleep state printed was [DEBUG] prev_sleep_state 5 (S3) This patch corrects this by using ACPI sleep state numbers for mapping the prev_sleep_state values. TEST=test the logs on google/rex board after cold reset [DEBUG] prev_sleep_state 5 (S5) Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I9bcdacc4d01a8d827a6abdf9af2b9e5d686ed847 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80144 Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-19device/Kconfig: Move Intel/ACPI/USB4 specific Kconfig optionsArthur Heymans
This options should not be visible on !Intel, !ACPI and !USB4. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ia515d52baead9e151533278c33fda9436ee56168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79669 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22soc/intel/cmn/block/smm: Clear SPI SYNC_SS before disabling WPDSubrata Banik
This patch follows the BWG recommendation (doc 729123) by clearing the SPI SYNC_SS bit before disabling the WPD bit in SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error. Unable to follow this guideline would result into boot hang (3-strike error). BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex. Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22soc/intel/cmn/block/pmc: Add previous sleep state strings in logMarx Wang
Previous sleep state showing in serial log is a magic number. In order to let users understand its meanings directly, add the strings to describe the modes. TEST=build, boot the device and check the logs: without this change, the log is like: [DEBUG] prev_sleep_state 0 with this change: [DEBUG] prev_sleep_state 0 (S0) Change-Id: Iabe63610d3416b3b6e823746e3ccc5116fabb17d Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-22x86: Separate CPU and SoC physical address sizeJeremy Compostella
The physical address size of the System-on-Chip (SoC) can be different from the CPU physical address size. These two different physical address sizes should be used for settings of their respective field. For instance, the physical address size related to the CPU should be used for MTRR programming while the physical address size of the SoC should be used for MMIO resource allocation. Typically, on Meteor Lake, the CPUs physical address size is 46 if TME is disabled and 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. As a result, MTRRs should reflect the TME status while coreboot MMIO resource allocator should always use 42 bits. This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the physical address size of the SoC for those SoCs. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Icb76242718581357e5c62c2465690cf489cb1375 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20soc/intel/common,mtl: Refactor BERT generation flow for crashlogPratikkumar Prajapati
With earlier flow, a chunk of CBMEM region was allocated for each SRAM e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM content was copied to dedicated CBMEM region. Later in acpi_bert.c, the BERT table was getting created for each chunk of CBMEM. This flow was not considering creating separate entries for each region of crashlog records. It resulted in only the first entry getting decoded from each SRAM. New flow aims to fix this issue. With new flow, a simple singly linked list is created to store each region of crashlog records from all SRAMs. The crashlog data is not copied to CBMEM. The nodes are allocated dynamically and then copied to ACPI BERT table and then freed. This flow also makes the overall crashlog code much simpler. BUG=b:298234592 TEST=With this change decoding crashlog show comprehensive details, tested on REX. Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78257 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-15soc/intel/cmn/cpu: Introduce API to disable signaling 3-strike eventSubrata Banik
This patch introduces a new API to disable signaling the 3-strike event on Intel Meteor Lake C0 (QS) stepping and subsequent SoCs. This is necessary because the existing event handling mechanism is incompatible with the new hardware design. Disabling the 3-strike event registration prevents the 3-strike count from increasing, which addresses bug b:314883362. This issue can potentially lead to system instability. BUG=b:314883362 TEST=disabling the 3-strike event on a Google Screebo system with QS silicon. Change-Id: I15bd5a93da34d7f2a127c21c4cd8b5952926bccf Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79472 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-11soc/intel/cse: Add API to check if CSE Firmware update is requiredAnil Kumar
This patch adds a function to check if a CSE FW update is required during this boot. The function is expected to be used during use cases like Pre-Memory Sign of Life text display to inform user of a CSE Firmware update. Bug=279173035 TEST=build and boot on google/rex board. Call the function in romstage and confirm it returns True during CSE FW update and False otherwise Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: If5fae95786d28d586566881bc4436812754636ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/78243 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-14soc/intel/cmn/block/cse: Support sending EOP from payloadKapil Porwal
Skip sending EOP from coreboot when payload is sending it. BUG=b:279184514 TEST=Verify sending EOP from depthcharge on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0fbb9fd0f8522eefad39960ca3167c2ba764f523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74765 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-10device/Kconfig: rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORTFelix Held
Rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORT and add a help text to this Kconfig option to clarify what this option is about. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71e36869c6ebf77f43ca78f5e451aebfb59f1c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-09Allow to build romstage sources inside the bootblockArthur Heymans
Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-03soc/intel/cmn/gfx: Join MBUS while FSP-S performs GFX initSubrata Banik
This patch calls into the function to join the MBUS if the GFX PEIM module inside the FSP binary is taking care of graphics initialization based on the RUN_FSP_GOP config option. The FW skips joining the MBUS in case of a non-FSP solution and/or SOC_INTEL_GFX_MBUS_JOIN config is not enabled. BUG=b:284799726 TEST=MBUS joining is only applicable for google/rex while using GFX PEIM. Change-Id: I50d719a286722f5aafbad48ab4ca60500c836dd6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-01soc/intel/cmn/gfx: Fix GFX modeset issue with dual-displaySubrata Banik
This patch fixes the redundent GFX modeset issue when a dual display is attached (e.g. an eDP display and an HDMI display). The issue was caused by the MBUS joining logic not considering the display type. This patch introduces three types of display: internal, external, and dual-display. The MBUS joining logic is then updated to consider the display type and ensure that the correct pipes are joined to the MBUS: For internal-only displays, only PIPE-A is joined to the MBUS. For external displays, no pipes are joined to the MBUS. For dual-displays, all available pipes are joined to the MBUS. BUG=b:284799726 TEST=Able to fix the redundent modeset issue when eDP and HDMI attached to the google/rex. Change-Id: Ie2a3b9f1212a9dcab2b7305078fe22ee35e7423c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78691 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27soc/intel/cse: remove cbfs_unverified_area_map() API in cse_liteRizwan Qureshi
With CBFS verification feature (CONFIG_VBOOT_CBFS_INTEGRATION) being enabled, we can now remove cbfs_unverified_area_map() APIs which are potential cause of security issues as they skip verification. These APIs were used earlier to skip verification and hence save boot time. With CBFS verification enabled, the files are verified only when being loaded so we can now use cbfs_cbmem_alloc()/cbfs_map function to load them. BUG=b:284382452 Change-Id: Ie0266e50463926b8d377825142afda7f44754eb7 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78214 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2023-10-25cbmem.h: Drop cbmem_possible_online in favor of ENV_HAS_CBMEMArthur Heymans
The macro ENV_HAS_CBMEM achieves the same as this inline function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6d65ca51c863abe2106f794398ddd7d7d9ac4b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77166 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2023-10-23soc/intel/common/acpi: Don't generate LPI constraints for disabled/hidden ↵Matt DeVillier
devices When walking the devicetree to generate the list of devices and minimum sleep states, skip any devices which have the disable or hidden flags set. This prevents adding entries for devices which are not present, which are hidden (and likely to not have a min sleep state entry), or generating duplicate entries in the case of PCIe remapping. Any of these conditions are considered invalid by Windows and will result in a BSOD with an INTERNAL_POWER_ERROR. TEST=tested with rest of patch train Change-Id: I06f64a72c82b9e03dc8af18700d24b3d10b7d3a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-23soc/intel/common/pcie: Disable removed RPs when updating devicetreeMatt DeVillier
If a root port is not present but was enabled in the devicetree, mark it disabled so that no ACPI references will be generated by any function which walks the devicetree (eg, LPI constraints). TEST=tested with rest of patch train Change-Id: I52e23fb1c0148a599ed736fc294e593ebbd27860 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78517 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-19soc/intel: Improve CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ useJeremy Compostella
Commit bd9c562a9e0c6af65f5e798a17ba9a55892ef082 ("acpi: Configure slp-s0 residency counter frequency in LPIT table") led to jenkins reporting the following error: !!!!! Error: defined(CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ) used at src/include/acpi/acpi.h:457. Symbols of type 'hex' are always defined. Since hex Kconfig are always defined there is no need to test it being defined but also no need to handle zero or non-zero values. In addition: 1. This config was defined in Meteor Lake specific Kconfig file while it should actually be define closer to where it is being used (here soc/intel/common/block/acpi/Kconfig) and only set by the SoC Kconfig. 2. Once moved and under control of `SOC_INTEL_COMMON_BLOCK_ACPI_LPIT' gating (lpit.c), the Kconfig name needed to be adjusted to better fit its use. 3. Make Meteor Lake Kconfig sets the config but does not define it anymore. TEST=LPIT ACPI table Counter Frequency field is set to 0x2005 on rex Change-Id: I2083c9209e61be6180cca2c9f74097e2f4b4ce9a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78458 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-18soc/intel/cmn/graphics: Implement API for IGD to join the MBUSSubrata Banik
This patch implements `.final` hooks for the IGD device to perform the required operations before handing the control to the payload or OS. The MBUS (Memory Bus) is a high-speed interface that connects the graphics controller to the system memory. It provides a dedicated data path for graphics data, which helps to improve graphics performance. The MBUS is a key technology that helps to make the Intel i915 driver powerful and versatile graphics drivers available. It provides the high-speed data transfer capabilities that are essential for smooth and responsive graphics performance. Enable this config to ensure that the Intel GFX controller joins the MBUS before the i915 driver is loaded. This is necessary to prevent the i915 driver from re-initializing the display if the firmware has already initialized it. Without this config, the i915 driver will initialize the display to bring up the login screen although the firmware has initialized the display using the GFX MMIO registers and framebuffer. Kernel graphics driver can avoid redundant display init by firmware, which can optimize boot time by ~15ms-30ms. Ensures hashing mode is 1x4 to enable a single pipe between Pipe A or B. Typically, internal display is on Pipe-A, so 1x4 restricts MBUS joining to internal display alone. BUG=b:284799726 TEST=Able to build and boot google/rex Change-Id: I60ae76dc783383e027e66edbcdeeb535472caeb1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78385 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-16soc/intel/cmn/gfx: Detect dual display (eDP + HDMI)Subrata Banik
This patch adds support for detecting dual displays (eDP and HDMI) on Intel platforms. This information is useful for setting the `lb_framebuffer.has_external_display` variable, which is used to determine whether depthchage should avoid shutting down when an extended display is present. TEST= Able to build and boot google/rex, where depthchage now successfully avoids shutting down when both eDP and HDMI displays are attached. w/o this patch: with eDP and HDMI attached: .has_external_display=0 with eDP attached: .has_external_display=0 with HDMI attached: .has_external_display=1 w/ this patch: with eDP and HDMI attached: .has_external_display = 1 with eDP attached: .has_external_display=0 with HDMI attached: .has_external_display=1 Change-Id: Ie39d48da75a21e3508a1fbcf09da31caedaa1c0a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78383 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-16soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BARMichał Żygowski
Reserve SBREG BAR if it is outside of the PCH reserved memory range. Desktop series processors have larger SBREG BARs, which, unlike mobile processors, do not fall into the standard PCH reserved range (0xfc800000 - 0xfe7fffff). Create a separate reservation for such a case. There is no telling what could happen if the reservation is not made in ACPI. TEST=Boot Windows 11 and Ubuntu 22.04 on MSI PRO Z690-A DDR4 Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77445 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-13soc/intel/cse: Remove unused header fileKrishna Prasad Bhat
Systemagent related functions are not used in this file. Remove the unused the header file. Change-Id: Ifbb04898e9dcebef96d8c73771e66e0d6fabc7fb Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78312 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-05soc/intel: separate slp-s0 residency counter frequency in LPIT tableSukumar Ghorai
Intel platforms use Low Power Idle Table (LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped IO Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC. Whereas slp_s0 residency counter running in different frequency. BUG=b:300440936 TEST=check kernel cpuidle sysfs are created after kernel boot cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04soc/intel/cmn/gfx: Add API to report presence of external displaySubrata Banik
This patch implements an API to report the presence of an external display on Intel silicon. The API uses information from the transcoder and framebuffer to determine if an external display is connected. For example, if the transcoder is attached to any DDI ports other than DDI-A (eDP), and the framebuffer is initialized, then it is likely that an external display is present. This information can be used by payloads to determine whether or not to power on the display, even if eDP is not initialized. BUG=b:299137940 TEST=Build and boot google/rex Scenarios: Booting with eDP alone: has_external_display value is 0 Booting with eDP + HDMI: has_external_display value is 0 Booting with HDMI alone: has_external_display value is 1 Booting with USB-C display alone: has_external_display value is 1 Change-Id: I77436940978c7fa9368d79394b46a5e794c32e42 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78080 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04soc/intel: Move USB wake methods to a common ASL fileReka Norman
The ACPI methods for enabling USB wake are identical on ADL, CNL and SKL. Move them to a common ASL file so they can be reused more easily on other SoCs. Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks in devicetree to a common header. BUG=b:300844110 TEST=Use abuild to build kinox, puff, and fizz with and without this change. Check the generated dsdt.aml is unchanged. Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-04soc/intel/cse: Add entries to eventlog on PSR backup eventsKrishna Prasad Bhat
This patch adds eventlog entries for the below scenarios: 1. To indicate success or failure of PSR data back-up command 2. To indicate the loss of PSR data when CSE update is corrupted, and data clear command is issued to clear the data. 3. To indicate the loss of PSR data when CSE boot partition info response is corrupted and data back-up is not initiated. BRANCH=None BUG=b:273207144 TEST=Verify elog event added after PSR data backup command is sent cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent ... ELOG: Event(B9) added with size 10 at 2023-06-27 06:44:49 UTC Change-Id: I2459a2b941d28a87b6c78f75dbe8779d73328d7a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04soc/intel/cse: Check PSR bit before issuing PSR backup commandAnil Kumar
Get PSR bit state using MKHI_FWCAPS_GET_FW_FEATURE_STATE HECI command Use this bit info to check if SKU supports PSR and consequently issue PSR_HECI_FW_DOWNGRADE_BACKUP command for PSR data backup during downgrade. BUG=b:273207144 TEST=build CB image and boot on google/rex board. Check for "PSR is supported in this SKU" message in coreboot logs to confirm that PSR bit is set in SKU Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04soc/intel/cse: Back up PSR data during CSE FW downgradeAnil Kumar
During CSE FW downgrade we erase CSE data. This would result in Platform Service Record(PSR) data also to be erased. To avoid losing PSR data we need to make a backup before data clear. This patch sends PSR_HECI_FW_DOWNGRADE_BACKUP HECI command to CSE, informing the CSE to backup PSR data before a data clear operation during downgrade. CMOS memory is used to track the backup status. PENDING is the default state, it is updated to DONE once PSR_HECI_FW_DOWNGRADE_BACKUP HECI command is sent. PSR data can be backed up only post DRAM is initialized. The idea is to perform cse_fw_sync actions in ramstage when PSR is enabled on a platform. As part of the cse_fw_sync actions, when a firmware downgrade is requested the command to back-up data is sent. Once the backup has been done, trigger the firmware downgrade. BRANCH=None BUG=b:273207144 TEST=build CB image for google/rex board and check PSR backup command is being sent during a CSE FW downgrade. Also check PSR data is not lost/erased after a downgrade using intel PSR tool. Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74577 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/intel/cse: Implement APIs to access PSR backup status in CMOSKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data. Since firmware downgrade and PSR data backup flows involve global resets, there is a need to track the PSR data backup status across resets. So adding a CMOS variable for the same. This patch implements API to access PSR backup status stored in CMOS. The get API allows to retrieve the PSR backup status from CMOS memory. The update API allows to update the PSR backup status in CMOS. BRANCH=None BUG=b:273207144 TEST=Able to retrieve PSR backup status across resets. Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04soc/intel/cse: Add function to get cse_bp_info earlyKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data, and this command can be sent only in post-RAM stages. So the cse_fw_sync actions needs to be moved to ramstage. Sending cse_get_bp_info command in ramstage takes additional boot time of ~45-55ms on rex. To avoid the boot time penalty, this patch provides an API to get the cse_bp_info in early romstage. The response data is then migrated to cbmem once memory is initialized. The same data in cbmem can be utilized in ramstage to perform other cse_fw_sync actions. This patch also adds check to validate cse_bp_info in cbmem and avoids sending the command again if the data is valid. BUG=b:273207144 TEST=Verify the command works in early romstage, data is migrated to cbmem and valid data is available in ramstage on rex. Change-Id: Ib1e72c950ba0f4911924805f501ec1bd54b6ba3c Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78053 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/intel/cse: Select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE when PSR enabledKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data, and this command can be sent only in post-RAM stages. So the cse_fw_sync actions needs to be moved to ramstage. This patch ensures SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE is selected when PSR is enabled. BUG=b:273207144 Change-Id: I7c9bf8b8606cf68ec798ff35129e92cd60bbb137 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78055 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23soc/intel/cse: Move cse_store_rw_fw_version from cse_print_boot_partition_infoKrishna P Bhat D
cse_store_rw_fw_version() stores CSE RW firmware version in global variable or cbmem in romstage and ramstage respectively, based on the stage it is called in. The call to this function is from the cse_print_boot_partition_info() in cse_get_bp_info. In the subsequent patches, the idea is to send the cse_get_bp_info early in romstage and store in cbmem once memory is initialized. So when the cse_fw_sync is called in early ramstage, the stored cse_bp_info_rsp is used instead of sending the CSE get boot partition info command again. To de-link the call to cse_store_rw_fw_version from cse_get_bp_info and to ensure the CSE RW FW version is stored in all cases, moving the function to do_cse_fw_sync. BUG=b:273207144 Change-Id: I0add2c167c85cbddef2ecb4c019061a08562bbdf Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
2023-09-23soc/intel/cse: Make cse_bp_info response globalKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. CSE Lite SKU firmware supports a command to backup PSR data before initiating a firmware downgrade. PSR data backup command works only after memory has been initialized. Moving only the downgrade would add complexity of splitting the cse_fw_sync across pre-RAM and post-RAM stages. So the idea is to move cse_fw_sync into ramstage when PSR is enabled. We are introducing a flow to get CSE boot partition info in early romstage and then same data will be stored in cbmem once DRAM is initialized. The CSE BP info data in cbmem will be utilized in early ramstage to perform cse firmware sync operations. This helps in avoiding re-sending the CSE get boot partition info command in ramstage. Having cse_bp_info_rsp as global helps in de-linking cse_get_bp_info from cse_fw_sync. Many functions take cse_bp_info as input parameter. Since cse_bp_info_rsp is global now, we can make use of global cse_bp_info and remove it as input parameter from those functions. BUG=b:273207144 TEST=Verify cse_bp_info_rsp holds value across the stage. Change-Id: I0ee050b49fcae574882378b94329c36a228e6815 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77070 Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
2023-09-22Revert "soc/intel/common/block/cse/Kconfig: Remove unused symbols"Reka Norman
This reverts commit 06cb756f0202d78d299b30728b6559f6107c43c3. Reason for revert: These Kconfigs are needed by boards which use the CSE stitching tools (i.e. select STITCH_ME_BIN). They're selected by some boards in the downstream ChromeOS repo. They're used in src/soc/intel/Makefile.inc (see the line with `$(CONFIG_CSE_$(2)_FILE)`). Change-Id: Ide6fc74b457439f06b7ef9b37f11d6c9ff226b80 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76719 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-20intelblocks/oc_wdt: Consolidate the APIMichał Żygowski
Reduce the OC WDT integration code footprint by consolidating multiple API calls into a single function to be called by SoC. Change-Id: Iba031cd8e0b72cabc4d0d8a216273d763231c889 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77574 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18soc/intel: Update Raptor Lake graphics device IDsBora Guvendik
Added Raptor Lake U graphics device ids. Renamed Raptor Lake U graphics device ids that were marked as Raptor Lake P. Added Raptor Lake P graphics device ids. References: RaptorLake External Design Specification Volume 1 (640555) TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I44734f927764f872b89e3805a47d16c1ffa28865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77898 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-17soc/intel/common: Add more fields for CPU crashlog headerPratikkumar Prajapati
Add more details in CPU crashlog header structure, such as storage off status and support, re-arm status etc. These fields are used to check of particular feature is supported or not and if supported what is the status of the feature. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: I4242b6043b8f8ad9212780f44ca0448cd2b6b9f8 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77562 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-17soc/intel/common: Add cleanup and rearm functionsPratikkumar Prajapati
Introduce cpu_cl_cleanup() and cpu_cl_rearm() functions for CPU crashlog flow. Also add default weak implementations. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: Iad68d3fdaf7061148b184371f7ef87d83f2b2b38 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77238 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-17soc/intel/common: Make common cpu_cl_clear_data() weakPratikkumar Prajapati
Not all SOC follow the same programming to clear crashlog data. So make common implementation of cpu_cl_clear_data() weak. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: Ic2b4631d57703abff0ab1880fb272ef67bb1b8e9 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-15intelblocks/{pmc,p2sb}: Add missing RPL-S PCH IDs for PMC and P2SBMichał Żygowski
The PMC and P2SB IDs for Raptor Lake-S PCH were missing. Add them based on doc 619362 rev 2.2. Change-Id: I5de00adf2d87cf50571abb02b28e7feebdc3911e Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77448 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-15soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold bootDinesh Gehlot
This patch addresses the increased boot time issue that occurs when ISH store is enabled, such as in the "rex4es_ec_ish" variant. During a cold reboot, the CBMEM memory resets and loses the stored firmware versions. This causes the firmware versions to be fetched again from the CSE, which increases the boot time by about 200 ms. This patch stores a backup of the firmware version in CMOS and updates the CBMEM memory during a cold reboot. BUG=b:280722061 Test=Verified the changes on rex board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75755 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15soc/intel/cmd/blk/cse: Implement APIs to access CMOS CSE FPT versionsDinesh Gehlot
This patch implements APIs to access the CSE FW partition versions in CMOS. The get API allows users to retrieve the current version from CMOS memory. The set API allows users to set the version in CMOS memory. BUG=b:280722061 TEST=APIs verified on rex board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2023-09-14x86: Add .data section support for pre-memory stagesJeremy Compostella
x86 pre-memory stages do not support the `.data` section and as a result developers are required to include runtime initialization code instead of relying on C global variable definition. To illustrate the impact of this lack of `.data` section support, here are two limitations I personally ran into: 1. The inclusion of libgfxinit in romstage for Raptor Lake has required some changes in libgfxinit to ensure data is initialized at runtime. In addition, we had to manually map some `.data` symbols in the `_bss` region. 2. CBFS cache is currently not supported in pre-memory stages and enabling it would require to add an initialization function and find a generic spot to call it. Other platforms do not have that limitation. Hence, resolving it would help to align code and reduce compilation based restriction (cf. the use of `ENV_HAS_DATA_SECTION` compilation flag in various places of coreboot code). We identified three cases to consider: 1. eXecute-In-Place pre-memory stages - code is in SPINOR - data is also stored in SPINOR but must be linked in Cache-As-RAM and copied there at runtime 2. `bootblock` stage is a bit different as it uses Cache-As-Ram but the memory mapping and its entry code different 3. pre-memory stages loaded in and executed from Cache-As-RAM (cf. `CONFIG_NO_XIP_EARLY_STAGES`). eXecute-In-Place pre-memory stages (#1) require the creation of a new ELF segment as the code segment Virtual Memory Address and Load Memory Address are identical but the data needs to be linked in cache-As-RAM (VMA) but to be stored right after the code (LMA). Here is the output `readelf --segments` on a `romstage.debug` ELF binary. Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x02000000 0x02000000 0x21960 0x21960 R E 0x20 LOAD 0x0219e0 0xfefb1640 0x02021960 0x00018 0x00018 RW 0x4 Section to Segment mapping: Segment Sections... 00 .text 01 .data Segment 0 `VirtAddr` and `PhysAddr` are at the same address while they are totally different for the Segment 1 holding the `.data` section. Since we need the data section `VirtAddr` to be in the Cache-As-Ram and its `PhysAddr` right after the `.text` section, the use of a new segment is mandatory. `bootblock` (#2) also uses this new segment to store the data right after the code and load it to Cache-As-RAM at runtime. However, the code involved is different. Not eXecute-In-Place pre-memory stages (#3) do not really need any special work other than enabling a data section as the code and data VMA / LMA translation vector is the same. TEST=#1 and #2 verified on rex and qemu 32 and 64 bits: - The `bootblock.debug`, `romstage.debug` and `verstage.debug` all have data stored at the end of the `.text` section and code to copy the data content to the Cache-As-RAM. - The CBFS stages included in the final image has not improperly relocated any of the `.data` section symbol. - Test purposes global data symbols we added in bootblock, romstage and verstage are properly accessible at runtime #3: for "Intel Apollolake DDR3 RVP1" board, we verified that the generated romstage ELF includes a .data section similarly to a regular memory enabled stage. Change-Id: I030407fcc72776e59def476daa5b86ad0495debe Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-09-14chromeos/cse_board_reset.c: Clear EC AP_IDLE flagDerek Huang
When CSE jumps between RO and RW, it triggers global reset so the AP goes down to S5 and back to S0. For Chromebox, when AP goes down to S5 EC set AP_IDLE flag. This cause an issue to warm reset the Chromebox device when it is in recovery mode and powered by USB-C adapter. This patch allows AP to direct EC to clear AP_IDLE flag before trigger reset. BUG=b:296173534 BRANCH=firmware-dedede-136-6.B TEST=Chromebox DUT which is powered by USB-C adapter boots up after warm reset in recovery mode Change-Id: Ib0002c1b8313c6f25d2b8767c60639aed8a4f904 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77632 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
2023-09-12soc/intel/common: Fix invalid MADT entries creationJeremy Compostella
commit f8ac3dda02f22ebf857efb5b845db97f00598f7d ("soc/intel/common: Order the CPUs based on their APIC IDs") sort algorithnm walks all the `cpu_info' entries without discarding empty ones. Since `cpu_info' is not initialized, the data that is used is undefined and it generally results in the creation of invalid `Local x2APIC' entries in the MADT ("APIC") ACPI table. Depending on the X2APIC ID value the Linux kernel behavior changes (cf. arch/x86/kernel/acpi/boot.c::acpi_register_lapic()): 1. If (int)ID >= MAX_LOCAL_APIC (32768), the Linux kernel discards the entry with the "skipped apicid that is too big" INFO level message. 2. If (int)ID < MAX_LOCAL_APIC (32768) (including negative) this data is taken into account and it can lead to undesirable behavior such as core being disabled as (cf. "native_cpu_up: bad cpu" ERROR kernel message). TEST=Verified the MADT does not contain any invalid entries on rex. Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77615 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2023-09-12cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella
It makes the detection of this feature accessible without the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency. BUG=288978352 TEST=compilation Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11soc/intel: Remove space between function name and '('Elyes Haouas
Change-Id: I1dbfca33c437c680118eb3a92e60b5607c93e565 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77768 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-06soc/intel/common/block/acpi: Change __attribute__((weak)) to __weakElyes Haouas
Change-Id: I9ecd81ffaa48dbed225a23900704b259569cb7c8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77527 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01soc/intel/common/acpi: Add stub for GNA scoring acceleratorMatt DeVillier
Allows boards which enable the GNA device to provide an attachment point for the OS drivers. TEST=tested with rest of patch train Change-Id: I3398eefb80e4407594883dd39128cd7885105ac3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-01soc/intel/common: Rename crashlog macrosPratikkumar Prajapati
Remove MAILBOX word from CPU_CRASHLOG_MAILBOX_WAIT_STALL and CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT macros, because they can be used for other interface as well. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: I62b04fa4b05c427db494a536ca6504db02dfeb68 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77236 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01soc/intel/common: Add metadata tag definition for crashlogPratikkumar Prajapati
When parsing descriptor table the record can have tag type = 7. This tag contains metadata depending on SOC. The platform may choose to parse it based on implementation of crashlog. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: I60dda06950974f7949fa5635141e4b7798c4d1f2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-01soc/intel/cpu: Only show MP PPI option when meaningfulArthur Heymans
Older FSP releases don't have an option to do MP init via PPI, so it should not be visible. Change-Id: I74b4bd5dd72980b859763e89ead7d7f619321e66 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63759 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 13:28:17 +0000