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2024-10-01soc/intel: Correct return type of fsp_get_pch_reset_status()Subrata Banik
The `fsp_get_pch_reset_status()` function returns a FSP reset status code. This change corrects its return type from `uint32_t` to `efi_return_status_t` to ensure consistency with the FSP API and prevent potential issues caused by type mismatch. This correction is necessary for compatibility with both 32-bit and 64-bit FSP interfaces. The change also updates all callers of this function in the Meteor Lake and Panther Lake SoCs to use the correct return type. Includes `fsp/api.h` to provide the `efi_return_status_t` definition. BUG=b:347669091 TEST=Verified global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84571 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01soc/intel/common/cnvi: Add CNMT MutexSean Rhodes
Add "CNMT" Mutex, that will be used by the Bluetooth and CNVi driver. Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84598 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30soc/intel/common: systemagent: Fix typo in HAVE_BDSM_BGSM_REGISTER help textPaul Menzel
regist*re*s → regist*er*s Change-Id: Ie5f5cb481f0fac335e592fd3f1f56d5462e37c1e Fixes: 2b0b2ef9a258 ("soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-09-27driver/intel/ish: Add config to indicate the presence of ISH MAIN firmwareJayvik Desai
This commit introduces a new config DRIVER_INTEL_ISH_HAS_MAIN_FW to indicate that the Intel Sensor Hub (ISH) is using the ISH MAIN firmware. The ISH MAIN firmware is located in rootfs, hence we no longer need to store the ISH BUP version in the CSE partition. When this config is enabled, fetching the ISH BUP version from the CSE firmware partition is skipped. BUG=b:360144613 TEST=Local build successful and tested on trulo by toggling the config. Enabling this config skips printing the ISH version in cbmem. Change-Id: I6cacf7b44ce6895ecb96db295d184c7b7d5a872c Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84493 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-09-24soc/intel/common/block/lpc: Support IBL eSPIShuo Liu
IBL eSPI should be correctly configured by LPC driver so that console input is usable. Change-Id: I77cc6dd67b36035974e7f268d32b8473e8d83483 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-09-24soc/intel/meminit: Check array sizeArthur Heymans
Work around a GCC LTO bug. Even if no buffer overflow is bound to happen as the soldered down path is taken GCC LTO complains about this. Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-20soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT tableCliff Huang
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block rather than checking if GPE1_STS(0) is '0'. BUG:362310295 TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check that FADT table includes GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Without the flag, boot to OS and check that FADT table does not include GPE1. FADT should have: GPE1 Block Address : 0 GPE1 Block Length : 0 GPE1 Base Offset : 0 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-19soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMICliff Huang
In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in northbridge.asl if DMI_BASE_SIZE is '0' BUG=b:348678529 TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot to OS and check ACPI PDRC device from the ACPI DSDT table. There should not have an entry for DMI in its _CRS method. Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/84349 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-18soc/intel: Move CSE update ELOG to cse_lite.cSubrata Banik
The ELOG for CSE updates was being added in fsp_params.c, but the actual update happens in cse_lite.c. This commit moves the ELOG to cse_lite.c to more accurately reflect where the event is happening. This also removes the need for a sol_type variable in meteorlake/romstage/fsp_params.c. It also helps to avoid redundant ELOG event entry while performing CSE update (due to CSE RO to RW switch dependency). BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo) TEST=Able to see only one instance of ELOG while performimg CSE sync. w/o this patch: elogtool list 0 | Log area cleared | 4088 1 | Kernel Event | Clean Shutdown 2 | Early Sign of Life | MRC Early SOL Screen Shown 3 | Early Sign of Life | CSE Sync Early SOL Screen Shown 4 | System boot | 29 5 | Memory Cache Update | Normal | Success 6 | Early Sign of Life | CSE Sync Early SOL Screen Shown w/ this patch: elogtool list 0 | Log area cleared | 4088 1 | Early Sign of Life | MRC Early SOL Screen Shown 2 | Memory Cache Update | Normal | Success 3 | System boot | 30 4 | Memory Cache Update | Normal | Success 5 | Early Sign of Life | CSE Sync Early SOL Screen Shown Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-09-13soc/intel/cmn/block/cpu: Simplify calculation of non-eviction waysSubrata Banik
The calculation of non-eviction ways (used for cache-as-ram configuration) has been simplified by removing conditional move instructions and directly adding the remainder to the quotient. This achieves the same ceiling operation but with potentially improved efficiency (less instructions). No functional changes are expected. TEST=Able to build and boot google/rex. Change-Id: I7cf5ff19ec440d049edc3bf52c660dea96b1f08a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-09-11soc/intel/cml, pci_ids: Remove IDs of non-existent graphics devicesMaxim Polyakov
These identifiers are not included in the GPU list from Intel [1]. At the same time, 0x9B44 is not PCI DID of graphics device at all: 8086:9B44 - 10th Gen Core Processor Host Bridge/DRAM Registers [2]. [1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html [2] https://web.archive.org/web/20231004011832/https://devicehunt.com/ view/type/pci/vendor/8086/device/9B44 Change-Id: I8ff7b062f930cb63ffd9caf240874742bd53fc23 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-07soc/intel/{common,alderlake}: Add missing ADL-N SKUsMichał Żygowski
Based on DOC #767454 (public) version 1.2. Allows to boot the HARDKERNEL ODROID H4+ with N97 SoC. Without this patch the MCH ID was not recognized and the SA driver did not pick up the stolen ranges, causing the PCI MMIO allocation to be placed in the stolen areas. TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04. Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84212 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-06soc/intel/common/gpio: vm index changes as PTL vm entries are not continuousCliff Huang
Add specific virtual wire mapping structure for: - First pad group does not starts with bit position 0. - vw_index and position are not continuous in between groups within a community. BUG= TEST=boot to OS and use iotools to read the registers that use 16-bit port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group ID field. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I986d4f4fe59b110e5075cab8742dfe8b336d034b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-05soc/intel/common/systemagent: Fix grammer in commentsYuchi Chen
Change-Id: I62d0e324329fdde599e67efb23f813e3b3c650ef Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84199 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-09-05soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT tableCliff Huang
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Reviewed-on: https://review.coreboot.org/c/coreboot/+/84103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-04soc/intel: Refactor ITSS macrosSubrata Banik
This patch refactors ITSS related SoC specific macros by consolidating them into a common itss.h file. This improves code maintainability and reduces redundancy as each SoC previously defined the same macros. Specific changes include: - Move SoC specific ITSS macros into intelblocks/itss.h. - SoC code now includes intelblocks/itss.h instead of the SoC-local soc/itss.h. - Drop soc/itss.h from static ASL files. - Delete soc/itss.h from all SoC locals except Apollo Lake and Sky Lake. TEST=Able to build and boot google/hatch, google/xol and google/karis. Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-09-04soc/intel/common/block: Include register offsets for POWER_CTLSaurabh Mishra
Details: - Add (POWER_CTL) – Offset 0x1fc required bits. Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2024-09-04tree: Drop unnecessary "true/false" commentsElyes Haouas
Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-02soc/intel/common/systemagent: read sa resources only from domain 0Yuchi Chen
Change-Id: Ida4461de6275bdd314f5cba441d3ff631d570305 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-09-02soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by KconfigYuchi Chen
CAPID_A, BDSM and BGSM registers may not exist on specific platform, this patch add `HAVE_CAPID_A_REGISTER` and `HAVE_BDSM_BGSM_REGISTER` to select them. Change-Id: I4d1197b8b1071aefc2ea1ed2f707d769aabab5e4 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-09-02soc/intel/common/gpio: support 16-bit CPU Port IDCliff Huang
- Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID. - Change cpu_port field to 16-bit width if the Kconfig is set. BUG=none TEST=boot to OS and use iotools to read the registers that use 16-bit port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group ID field. The bit 15:8 of the returned port ID value should be 0xF2 instead of zero. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83981 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-30soc/intel/pmclib.c: Work around compiler bug -Werror=stringop-overreadArthur Heymans
On xeon-sp this is a zero length array. With GCC LTO this triggers the stringop-overread warning. To work around this change the signature of the function from an array to a pointer. Change-Id: Ieee6e9bddc4e738eb560dd0e69dc3087ac9f5da6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-22soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdrCliff Huang
These field defines are SOC-specific. The AUX bias virtual wire field positons are shifted in PTL. In MTL SOC and older: 7:0 GROUP_ID Group ID in PCH GPIO 10:8 BIT_NUM Data bit Position in PCH GPIO 23:16 VW_INDEX VW Index in PCH GPIO In PTL SOC: 15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID 18:16 BIT_NUM Data bit Position in PCH GPIO 31:24 VW_INDEX VW Index in PCH GPIO BUG=361048817 TEST=boot to OS and use iotools to read AUX Bias Ctrl register to verify the group ID, bit number, and vw index. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83980 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-08-21soc/intel/cmn/pmc: Add pmc_ipc to bootblockJamie Ryu
This adds pmc_ipc to bootblock if SOC_INTEL_COMMON_BLOCK_PMC is enabled. The good place to report SoC QDF can be report_cpu_info in bootblock. QDF read is done by PMC IPC Command, so this adds pmc_ipc to bootblock to enable calling pmc_dump_soc_qdf_info. Change-Id: Id0391eae48fc53cd652acd09e6380ca6802eaf88 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-21soc/intel/common/block/cpu: Round up the number of waysJeremy Compostella
`CONFIG_DCACHE_RAM_SIZE' is not necessarily a multiple of way size. As a result, when the `div' instruction is called to compute the needed number of ways, there could be a remainder. When there is, one extra way should be added to cover `CONFIG_DCACHE_RAM_SIZE'. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83982 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/common/block/cpu: Fix ways count computation regressionJeremy Compostella
Commit 16ab9bdcd578612bb3822373547f939eb90afd82 ("soc/intel/common: Calculate and configure SF Mask 2") breaks the computation of the number of ways and as result, all the derived masks. It results in MSR such as `IA32_L3_MASK_1' to be improperly programmed yielding unpredictable NEM issues such as hangs. Indeed, this commit has introduced a backup of 0x1 into %edx before comparing the requested cache-as-RAM size against the way size. When the requested cache-as-RAM is larger, it reaches the second part of the algorithm which computes the necessary number of ways to fit the requested cache-as-RAM. This algorithm uses the `div' instruction. Per specification, the div instruction divides the 64 bits combination of %edx and %eax register. Since 0x1 got backed up in %edx and assuming a `CONFIG_DCACHE_RAM_SIZE' of 0x200000, we end up dividing 0x100200000 by the way size instead of 0x200000 which result in a necessary number of ways of 4098 for a way size of 0x100000. This commit clears the %edx register before calling the `div' instruction. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521d Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83948 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/common: fix CrashLog size in legacy modeJędrzej Ciupis
Intel's PMC CrashLog size in legacy mode is expressed in DWORDs and therefore needs to be explicitly recalculated to bytes. BUG=None TEST=Built and checked the size in logs Change-Id: I2678d537439c24fbd10aa3ceffee63c9a849d28b Signed-off-by: Jędrzej Ciupis <jciupis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-20soc/intel/cmn/basecode/debug: Add SOC_INTEL_COMMON_DEBUG_CONSENT configSubrata Banik
This patch adds a generic config option, SOC_INTEL_COMMON_DEBUG_CONSENT, to control the debug interface on Intel SoCs. This eliminates the need for SoC-specific config options like SOC_INTEL_<SOC_NAME>_DEBUG_CONSENT. Default values are provided for various debug types: - 0: Disabled - 1: Enabled (DCI OOB + [DbC]) - 2: Enabled (DCI OOB) - 3: Enabled (USB3 DbC) - 4: Enabled (XDP/MIPI60) - 5: Enabled (USB2 DbC) - 6: Enabled (2-wire DCI OOB) - 7: Manual Specific SoCs can override the SOC_INTEL_COMMON_DEBUG_CONSENT value using SoC config override methods. TEST=Able to build google/rex. Change-Id: I84ad03f0ffe5da4bc53c665489c430fe9b65ede7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-11soc/intel/common/block/gpmr: Allow soc to have specific gpmr definitionYuchi Chen
This patch add a new Kconfig HAVE_SPECIFIC_GPMR and use it to include soc/gpmr.h if necessary. Change-Id: I94797a72af75fc96ab2cacb1d46b581605a15387 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83317 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11azalia: Get rid of "return {-1,0}Elyes Haouas
Use 'enum cb_err' instead of {-1,0}. Change-Id: Icea33ea3e6a5e3c7bbfedc29045026cd722ac23e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-10tree: Remove unused <smbios.h>Elyes Haouas
Change-Id: Iab7e9f3d17c87576761333c4b62c40eea5e424a5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-10soc/intel/common/block/gpio/gpio.c: Improve GPIO debug infosYuchi Chen
1. print host software ownership, SMI enable and NMI enable registers after configuring 2. read and print GPIO configuration dword registers after writing 3. use %zu to print size_t values according to CI reporting. Change-Id: I8820956f6db91c7bcc26b46a4361da3dfa8f77b5 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83316 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09device/pci_ids: Add new Intel PTL device IDs for TracehubBora Guvendik
This patch adds new North Peak PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the tracehub driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Boot to OS using PTL Silicon, verify if above 4GB IMR region is reserved. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ifa1a0a57c504e06d686e7e0826547251b456cc8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83786 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSIONSubrata Banik
This change adds support for specifying the CSE_RW_VERSION directly in Kconfig. * If `CONFIG_SOC_INTEL_CSE_RW_VERSION` is defined, its value will be used directly as the CSE_RW version. * Otherwise, the version will be extracted from the CSE_RW binary file as before. Platform prior to Intel Meteor Lake still requires to override the CSE RW version using CONFIG_SOC_INTEL_CSE_RW_VERSION config rather reading the CSE RW version from CSE RW partition. BUG=b:327842062 TEST=CSE RW update successful on Karis with this patch using below recipe: 1. Overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2269" 2. Without overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="" Platform prior to Intel Meteor Lake would be using #1 and platform starting with Meteor Lake expected to use #2 recipe. Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83831 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-09soc/intel/cmn/pmc: Add API to dump silicon QDF informationJamie Ryu
This adds pmc_dump_soc_qdf_info function and PMC_IPC_CMD_SOC_REG_ACC PMC IPC Command to read and print Intel SoC QDF information using PMC interface if SOC_QDF_DYNAMIC_READ_PMC is enabled. QDF read command is supported from Panther Lake SoC. QDF is a four digit code that can be used to identify enabled features and capabilities. This information will be useful to debug issues found during the development phase and in the field as well. Change-Id: I927da1a97e6dad4ee54c4d2256fea5813a0ce43d Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83784 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06intel/alderlake: Add helper functions for Power ManagementSean Rhodes
Clock Power Management, ASPM and L1 Substates have been configured the same way since Skylake. The main control to enable or disable is Kconfig, and then the level can be overridden in devicetree. Despite the UPDs remaining the same since Skylake, this is not the case for Alder Lake, Raptor Lake and Meteor Lake. Taking `starlabs/starbook` as an example, at the time of this commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE enabled. On Comet Lake, this results in the correct configuration, verified with the lspci command: ``` LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- ``` On Raptor Lake: ``` LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+ ``` Clock Power Management, ASPM and L1 Substates are also not configured for CPU root ports. Add helper functions to configure these correctly based on Kconfig, but retain the capability to override the specific levels from devicetree. Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81638 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-06soc/intel/common/intelblocks/gpio.h: Allow specifying the pad ownershipYuchi Chen
Add pad_own_reg_0 to `struct pad_community`. Pad ownership indicates whether the GPIO is owned by host or Intel Management Engine. If owned by host, then host ownership indicates whether the GPIO is owned by ACPI or driver. Change-Id: I30a934fd00a7a42cb156341da1954e4e4b1231d8 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83315 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platformYuchi Chen
CPU and PCIe IDs are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83314 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-02soc/intel/common/block/cse: Enforce CSE sync with pertinent GBB flagDinesh Gehlot
The patch enforces CSE sync when the GBB flag GBB_FLAG_FORCE_CSE_SYNC is enabled and the system is currently booting from the RO section. Additionally, it integrates forced CSE sync into eSOL decision-making. BUG=b:353053317 TEST=Verified forced CSE sync on rex0 with GBB 0x200000 Cq-Depend: chromium:5718196 Change-Id: I228bc8ebf58719776f6c39e0bfbb7ad53d9bfb7f Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for CNViSubrata Banik
This patch adds new CNVi PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the CNVi driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused BT PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I7d80403b87537aea41ff48ff6d274180577f1ac6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83520 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for XDCISubrata Banik
This patch adds new XDCI PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the XDCI driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused TCSS XDCI PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I51196401904e2402ac7669fa852a541bb7c2d453 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83518 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for CSE0Subrata Banik
This patch adds new CSE0 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the CSE0 driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused CSE1-3 PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5656aeb8c5439c8361aeb3a3d759df1216d84f8b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83517 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for AudioSubrata Banik
This patch adds new Audio (HDA/DSP) PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the Audio driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I3c9e420a6ae19d00fb5510c99d4c219dc43ad3c0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83516 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for SRAMSubrata Banik
This patch adds new SRAM PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SRAM driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ib6d62dad59965258dab453533dface9c359de586 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83515 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for P2SBxSubrata Banik
This patch adds new P2SBx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the P2SBx driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie1c36bc1c014bb1e219afe0cafb6c9941f253b0c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for XHCI/TCSS XHCISubrata Banik
This patch adds new XHCI/TCSS XHCI PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the XHCI driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5ae8f493374087a5e684e0a04486cd64cea6f335 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83513 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for SMBUSSubrata Banik
This patch adds new SMBUS PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SMBUS driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I4b8b59cf4e005f0e17a25d0fbe761404dab432b3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83512 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for Fast-SPI and GSPIxSubrata Banik
This patch adds new Fast-SPI and GSPIx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SPI driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5c7c0be6f219c93d4520494857d31ce1cf939f36 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83511 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for UARTxSubrata Banik
This patch adds new UARTx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the UART driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I384a753f08ae5a752cef6009d07104e8ff4b4a6e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for I2CxSubrata Banik
This patch adds new I2Cx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the I2C driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I79ba0b563146d658521cdd40aabb3ee882f4d187 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83509 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for PMCSubrata Banik
This patch adds new PMC PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the PMC driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Iae468fdace2d9cfd532957e4f3c55b89b96a52a0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83508 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for PCIeSubrata Banik
This patch adds new PCIe Root Port PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the PCIe driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5913c6ac0a4766c14f23954be1e885d45f69d36a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83507 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for eSPI/LPCSubrata Banik
This patch adds new eSPI/LPC PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the LPC driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie9f0ea9536e2f73c2258e9e12b510d21212248ea Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for DID2Subrata Banik
This patch adds new DID2 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the graphics driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Iab499070c87e020e36901b4ea453a1893bd16ea0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83491 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for DID0Subrata Banik
This patch adds new DID0 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the System Agent driver's `systemagent_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie4d77eb489e16d18b996fdda3216e1275083d7e7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83490 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18soc/intel/cmn/pch: Consolidate eSPI.h into IA common codeSubrata Banik
This patch moves the SoC-specific `eSPI.h` file into the IA common code to promote code reuse and reduce duplication across different SoC generations. TEST=Builds successfully for google/rex. Change-Id: Icb09421eec45c1ef8ab50252543b000078f18b21 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/cmn/cpu: Introduce common CAR APIsSubrata Banik
This patch adds `car_lib.c` to the IA common code to consolidate SoC-agnostic CAR APIs. Initially, it includes `car_report_cache_info()` to provide a unified way to read cache information, reducing the need for SoC-specific implementations. TEST=Builds successfully for google/rex. Change-Id: I2ff84b27736057d19d4ec68c9afcb9b22e778f55 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-12soc/intel: Adapt crashlog IP to also support 64-bitSowmya Aralguppe
This patch extends the crashlog IP support beyond 32-bit mode to support Intel future generation SoCs, which may require crashlog support for 64-bit architectures. uintptr_t data type is used for Address pointers and void* for dereferencing BUG=b:346676856 TEST=Successfully built Meteor Lake (rex) and tested for google/rex0 and google/rex64 images. Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83106 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12soc/intel/cmn/cse: Correct CMOS error message for CSE partition firmwareSubrata Banik
The CMOS entry for CSE partition firmware was incorrectly labeled as `ramtop` and `partition firmware` in the error messages. This patch corrects the messages to accurately refer to `CSE partition firmware`. Additionally, the alignment and size check comments are updated to reflect this change. Change-Id: Ib3a7fb88f52c4d0c47d828bcd1c4649e62d19654 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-11soc/intel/cmn/cse: Refine boot partition loggingSubrata Banik
This patch ensures CSE boot partition (RO/RW) version information only log when the status is "success". If the status is not successful, log an error message indicating the failure and status code. This change avoids logging potentially incorrect version information when the boot partition is not valid. BUG=b:305898363 TEST=Builds successfully for google/rex variants. Change-Id: I1932302b145326a1131d64b04af1cbfd6d050b7b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel: Extend CSE RW Update and ME read access for payload syncSubrata Banik
Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and `ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`. This allows these features to be enabled even when CSE sync is performed in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU` config is enabled). BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibilitySubrata Banik
This patch refactors the handling of CSE CBMEM IDs to enable platforms to choose whether to perform CSE sync operations within coreboot or defer it to the payload. This separation improves code organization, ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks. Now, platforms can select: * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync This change ensures mutually exclusive options, avoiding unnecessary SPI flash size increases. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10cbmem_top: Change the return value to uintptr_tElyes Haouas
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/common: Skip ME version log for Lite SKUSubrata Banik
This change skips the ME firmware version logging in print_me_fw_version() if the ME firmware SKU is detected as Lite SKU. The reasoning is that the RO (BP1) and RW (BP2) versions are already logged by the cse_print_boot_partition_info() function for Lite SKUs, making the additional log redundant. The check for the Lite SKU has been moved to print_me_fw_version(), where the decision to print the version is made, instead of in get_me_fw_version(), where the version information is retrieved. TEST=Able to build and boot google/rex. w/o this patch: [DEBUG] ME: Version: Unavailable w/ this patch: Unable to see such debug msg. Change-Id: Ic3843109326153d5060c2c4c25936aaa6b4cddda Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-03soc/intel/cmn/cse: Make ME firmware version query function staticSubrata Banik
This change modifies the get_me_fw_version() function to be statically scoped within src/soc/intel/common/block/cse/cse.c, as it is only used by the print_me_fw_version() function in the same file. The function declaration is also removed from intelblocks/cse.h. The order of the function definitions in cse.c was also changed to be more logical, with the now static helper function get_me_fw_version() defined first, before it is used. TEST=Able to build google/rex. Change-Id: Idd3a6431cfa824227361c7ed4f0d5300f1d04846 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83257 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/cmn/cse: Conditionally disable ME status reportingSubrata Banik
This patch disables the ME status reporting functionality (dump_me_status, print_me_fw_version) in the CSE driver when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is defined. This is likely intended for platforms or configurations where the CSE communication is only limited to payload. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5e360408a7847968117df475ff244d79ceafa23f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83233 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03soc/intel/cmn/cse: Skip CSE version call if sync is done by payloadSubrata Banik
This patch skips the CSE firmware version print when CSE sync is done by payload. The payload is responsible to dump the CSE version. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1a9e5583c79ebd81291a4b3ae24529b4582502cb Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03soc/intel/cmn/cse: Modify dependency on CSE EOP configsSubrata Banik
Refactor CSE lite End-of-Post (EOP) configs to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot will skip initiating CSE EOP operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_SEND_EOP_EARLY - SOC_INTEL_CSE_SEND_EOP_LATE - SOC_INTEL_CSE_SEND_EOP_ASYNC - SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD BUG=b:305898363 TEST=Able to build google/rex. Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83229 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/cmn/cse: Modify dependency on CSE lite configsSubrata Banik
Refactor CSE lite configs (specifically CSE sync related) to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot will skip initiating CSE sync operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_LITE_PSR - SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY - SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE - SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-06-28device/azalia_device.c: Always read-write GCAPAngel Pons
In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP register is RO (Read Only). However, it is known that in some Intel PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some of the bitfields in the GCAP register are R/WO (Read / Write Once). GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock bit for GCAP elsewhere. Lock GCAP by reading GCAP and writing back the same value. This has no effect on platforms that implement GCAP as a RO register or lock GCAP through a different mechanism. Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-25soc/intel/common: Extend WAIT_FOR_DP_MODE_ENTRY_TIMEOUT_MS to 1500msTony Huang
Some dongles require more time to be ready, this CL extedns the DP mode entry timeout from 0.5s to 1.5s and make sure the tested dongle display works. Before: [WARN ] DP not ready after 500ms. Abort. After: [INFO ] DP ready after 1211 ms BUG=b:348309582 TEST=emerge coreboot verify tested dongles and monitors display works Change-Id: I22d7800b50f6f7de9f147ae6998a5015d0dc0be9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83206 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-06-21soc/intel/cmn/block/cse: Create CBMEM entries for payload to fill with CSE infoKapil Porwal
Currently, the payload cannot create new CBMEM entries as there is no such infrastructure available. The Intel CSE driver in the payload needs below CBMEM entries - 1. CBMEM_ID_CSE_INFO to - a. Avoid reading ISH firmware version on consecutive boots. b. Track state of PSR data during CSE downgrade operation. 2. CBMEM_ID_CSE_BP_INFO to avoid reading CSE boot partition information on consecutive boots. The idea here is to create required CBMEM entries in coreboot so that later they can be consumed by the payload. BUG=b:305898363 TEST=Store CSE version info in CBMEM area in depthcharge on Screebo Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I9561884f7b9f24d9533d2c433b4f6d062c9b1585 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21soc/intel/cmn/acpi: Add support for `PCR_BASE_ADDRESS` above 4 GiBSubrata Banik
This change updates the Northbridge ASL to conditionally include a QWordMemory resource for `SM01` when the `CONFIG_PCR_BASE_ADDRESS` is above 4 GiB. If `CONFIG_PCR_BASE_ADDRESS` is below 4 GiB, or falls within the PCH reserved range, the existing handling of `SM01` remains unchanged (as a DWordMemory resource). TEST=Built with CONFIG_PCR_BASE_ADDRESS both above and below 4 GiB, verified ASL output. Change-Id: I9547377cdea6cb4334ab59b3bc837059fbb22e3b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83112 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-14soc/intel/common/block: Move VTd basic definitions into header fileJincheng Li
TEST=Build and boot on intel/archercity CRB Change-Id: I4f9e606cf9ec01ec157ef4dd7c26f6b5eb88c7b7 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07soc/intel/cmn/cse: Support CSE sync from payloadKapil Porwal
Skip CSE sync in coreboot when payload is doing it. BUG=b:305898363 TEST=Verify CSE sync from depthcharge on Screebo Change-Id: Ifa942576c803b8ec9e1e59c61917a14154fb94b2 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-06-07soc/intel/common/uart: Drop chip in favor of devicetree opsArthur Heymans
It is now possible to hook up device ops directly to devices in devicetree which removes the need for a fake chip. This also fixes Hermes booting as the PCI ops were incorrectly hooked up to a dummy device. The intel uart driver was requesting a resource from the generic device and died since it does not exist: [EMERG] GENERIC: 0.0 missing resource: 10 This was broken in commit b9165199c32a (mb/prodrive/hermes: Rework UART devicetree entry). Change-Id: I3b32d1cc52afaed2a321eea5815f2957fe730f79 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82940 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-03tree: Use calloc(n, sizeof(struct)) insteadof calloc(sizeof(struct), n)Elyes Haouas
Change-Id: I5e67e370d4eb8fe28227843bbca34db06ad84b26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82786 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-31soc/intel: Fix pointer size mismatch errors in crashlogAppukuttan V K
The crashlog code in intel/common/block and meteorlake soc was casting integer addresses directly to pointer types, which caused compilation errors in x86_64 bit builds. This commit fixes the issue by using uintptr_t for casting integer addresses to pointer types before dereferencing. BUG=b:329034258 TEST=Successfully build Meteor Lake (rex) in both x86_32 and x86_64 modes. Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82481 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14soc/intel/common: Add RPL tracehub supportAshish Kumar Mishra
Add PCI ID for RPL tracehub and update the PCI ID in the pci_device_ids[] in tracehub.c. Reference: Raptor Lake External Design Specification Volume 1 (640555) BUG=None TEST=Verified on brox Change-Id: I5d5c6c8ff44bcb5a7bbbd3e27a1577c169ecd6a9 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-14soc/intel/common: Add Panther Lake DIDsSaurabh Mishra
Reference: Panther Lake External Design Specification Volume 0.51 (815002) BUG=b:329787286 TEST=verified on Panther Lake Simics Platform. Change-Id: I941d6e1c8a697234b8e64a2523e60587897d7f7a Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81848 Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12soc/intel/lunarlake: Support stepping A0_2Saurabh Mishra
Details: - Add support for new Lunar Lake MCH ID 0x6410 - Add new CPU id 0xb06d1 Reference: Lunar Lake External Design Specification Volume 1 (734362) TEST=Build, boot the system and verfiy MCH-ID prints in bootblock stage. Below prints verified on Lunar Lake RVP board (lnlrvp). [DEBUG] MCH: device id 6410 (rev 02) is LunarLake M Change-Id: I976d7f269485633d835d204afa224736d71baaa8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81847 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-12soc/intel/common: Add Lunar Lake CNVI device IDsSaurabh Mishra
Without this patch, ACPI SSDT does not supports and lists CNVW. With this patch, verified "CNVW" in ACPI SSDT listing. Scope (\_SB.PCI0) { Device (CNVW) { Name (_ADR, 0x0000000000140003) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Reference: Lunar Lake External Design Specification Volume 1 (734362) BUG=b:329787286 TEST=verified on Lunar Lake RVP board (lnlrvp). Change-Id: I5a0a3fbc9f43a6a573e33fcf3901055e10faaed1 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81846 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06common/block/tcss: Add config for PDC<->PMC mux configurationKrishna Prasad Bhat
Introduce a new Kconfig to enable PD controller to PMC mux configuration. Selecting this config enables direct communication from PDC to PMC. TCSS_HAS_USBC_OPS enables USB-C operations via the EC. When SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION is selected, disable TCSS_HAS_USBC_OPS to avoid sending PMC commands from AP/EC. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: Ieeb503393418cdad43384be39ac49c93ba91e4db Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82077 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06block/fast_spi: Use read32p/write32p for SPI RWAshish Kumar Mishra
The current fast_spi code uses memcpy for rw. The SPI flash read/write has 4 byte limit, due to which the current 64 bit memcpy doesn't work. Hence update rw ops to use read32p/write32p. BUG=b:242829490 TEST=Verified MRC cache working on MTL 64-bit, future 64 bit platforms and RPL(brox/skolas) 32-bit platforms. Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-29soc/intel/cmn/graphics: Make DDI-A 4 lanes configurableAngel Pons
As described in Intel document 336464 (8th gen S series datasheet volume 1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2 lanes. This lets mainboards provide a VGA output without sacrificing one of the main 4-lane DDIs. Newer platforms seem to be lacking this. However, the way this is structured in coreboot does not allow boards to choose whether bifurcation should be enabled. Most boards in the tree do not use DDI-E (it doesn't exist on mobile platforms), but there are some boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to provide a VGA output. Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to specify whether a platform supports DDI-A bifurcation at all (do nothing otherwise, maintaining the original code's behaviour). If bifurcation is supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register. Change-Id: I516538db77509209d371f3f49c920476e06b052f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DIDMichał Kopeć
Found in a Clevo V560TU with Intel Core Ultra 155H Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82071 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-23soc/intel/alderlake: Add Twinlake graphics device IDsSowmya V
Add the graphics device IDs for Twinlake platform based on Platform External Design Specification. Document ID: 645548 BUG=b:326901448 TEST=Build tivviks and verify the IGD IDs. Change-Id: Ide008d5c5302bd589784bc917a2610c42a0fdee4 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82038 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-22drivers/intel/fsp2_0: Introduce fsp print helper macrosAppukuttan V K
This patch introduces fsp print helper macros to print `efi_return_status_t' with the appropriate format. These macros are now used for fsp debug prints with return status efi_return_status_t is defined as UINT64 or UNIT32 based on the selected architecture BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: If6342c4d40c76b702351070e424797c21138a4a9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81630 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12tree: Drop unused <cbmem.h>Elyes Haouas
Change-Id: If8be8dc26f2729f55dc6716e6d01e2b801d79e44 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-11soc/intel/**/fast_spi.c: Reorganize some statementsAngel Pons
Avoid calling `acpi_device_scope()` and `fast_spi_acpi_hid()` if the result won't be used. Also, reorder a condition so that compile-time constants appear first, so as to help the compiler optimize it out. Change-Id: I42ce55c2978ad9c593c359c5decd5842fb3a97a1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-10tree: Drop unused <elog.h>Elyes Haouas
Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04soc/intel/common/block/fast_spi: probe for 2nd flash componentMichał Żygowski
Fast SPI code assumes only one SPI flash is present. The SPI flash driver for older southbridges is able to detect multichip. See the spi_is_multichip() in src/southbridge/intel/common/spi.c. Some boards (e.g. Lenovo ThinkCentre M920 Tiny) still come with two chips populated instead of one. With this change, both chips are probed, and the correct total size is calculated. Otherwise, only the first one was probed, which resulted in an error such as: SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x1800000!! Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-04soc/intel/cache_as_ram_fsp.S: Drop unused preprocessing directivesArthur Heymans
Change-Id: I42bb15b8534d16401cd06ff803a8425221c5f3c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-04drivers/intel/fsp2_0: Support FSP-T in long modeArthur Heymans
Call into FSP-T using the protected mode wrapper and enter long mode in FSP-T support assembly code. TEST: Booted on ibm/sbp1 in long mode. Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-01intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASEShuo Liu
IBL (Integrated Boot Logic) provides a subset of server PCH logics for no-PCH solution. IBL is with limited features and registers exposed, PCIe root ports/USB/SATA/LAN support are removed. Change-Id: I8f3d64a2dd3b79ec5a9e4306f40b012b00387259 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81314 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30soc/intel: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-28cpu/x86: Link page tables in stage if possibleArthur Heymans
When switching back and forth between 32 to 64 bit mode, for example to call a 32-bits FSP or to call the payload, new page tables in the respective stage will be linked. The advantages of this approach are: - No need to determine a good place for page tables in CBFS that does not overlap. - Works with non memory mapped flash (however all coreboot targets currently do support this) - If later stages can use their own page tables which fits better with the vboot RO/RW flow A disadvantage is that it increases the stage size. This could be improved upon by using 1G pages and generating the pages at runtime. Note: qemu cannot have the page tables in the RO boot medium and needs to relocate them at runtime. This is why keeping the existing code with page tables in CBFS is done for now. TEST: Booted to payload on google/vilbox and qemu/q35 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 16:22:34 +0000