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2016-08-11soc/intel/common: Add support for serial console based ACPI debugSubrata Banik
This patch enables serial debug functionality for ASL code based on UART type(legacy/LPSS). From Skylake onwards all Intel platform uses LPSS based UART for serial console hence provide option to redirect ASL log over LPSS UART. Example: Name (OBJ, 0x12) APRT (OBJ) APRT ("CORE BOOT") Output: 0x12 CORE BOOT BUG=none BRANCH=none TEST=Built and boot kunimitsu to ensure to be able to get ASL console log. Change-Id: I18c65654b8eb1ac27af1f283d413376fd79d47db Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/16070 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-08soc/intel/common: fix gsmi handlerAaron Durbin
The gsmi_exec() expects the parameter to be a pointer to the 32-bit register storage of the SMI save state. The previous code was passing a pointer with the value obtained from the saved-state -- not a pointer to the storage of the register value. This bug causes gsmi to not log events because it's interrogating the parameter buffer itself as if it were a pointer. BUG=chrome-os-partner:55932 Change-Id: I37981424f1414edad1456b31cad1b99020d57db6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16087 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-01soc/intel/common: Fix build error in reset.cLee Leahy
Fix build error caused by macro substitution in the function definition when the Kconfig value HAVE_HARD_RESET is not selected. src/soc/intel/common/reset.c:36:21: error: macro "hard_reset" passed 1 arguments, but takes just 0 void hard_reset(void) ^ src/soc/intel/common/reset.c:37:1: error: expected '=', ',', ';', 'asm' or '__attribute__' before '{' token { ^ make: *** [build/bootblock/soc/intel/common/reset.o] Error 1 TEST=Build and run on Galileo Gen2 Change-Id: I793570e62a0e46cca86cc540c243e363896ceac7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15988 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-01soc/intel/common: Enable MTRR display during bootblock & postcarLee Leahy
Update Makefile.inc to allow MTRR display during bootblock and postcar. TEST=Build and run on Galileo Gen2 Change-Id: If12896df46b9edfc9fff3fab3a12d2dae23517a3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15990 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31src/soc: Capitalize CPU, ACPI, RAM and ROMElyes HAOUAS
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-29soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resumeAbhay Kumar
Do not pass VBT table to fsp in normal mode and S3 resume so that PEIM GFX will not get initialized. Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/14575 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-28intel/common: Add ASL code for DPTFShaunak Saha
This patch adds the common ASL code for Intel platforms. This is the basic ASL needed to add support for DPTF controlled devices. We are moving these commmon ASL files to src/soc/intel/common/acpi as these are same codes used in all Intel platforms and hence no need to duplicate. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I01078382a9008263c6ad99f6bf07558885af6a63 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15093 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28intel/common/opregion.c: only write 16 bytes to 16 byte fieldMartin Roth
Including the terminating null, 17 characters were being written to the field, overwriting the a byte of the size field. Fortunately, the size was updated soon after this. Fixes coverity warning 1229570 - Destination buffer too small. Change-Id: I39285a9283dd9a17d638afe5b2755c7e420d7698 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15889 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-28soc/intel/skylake: Add C entry bootblock supportSubrata Banik
List of activity performing in this patch - early PCH programming - early SA programming - early CPU programming - mainborad early gpio programming for UART and SPI - car setup - move chipset programming from verstage to post console BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x34 Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27soc/intel/common: Store MRC data in next available slot in the cacheFurquan Shaikh
Currently, coreboot performs an erase of the entire MRC cache region on flash if there is a version mismatch for the MRC data. Instead of doing that, store the new MRC data in the next available slot, if there is enough space available in the cache region. BUG=chrome-os-partner:55699 Change-Id: Ib24a94f0a47c79941ed9f60095360ae3aad5540b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15915 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27cpu/x86: Support CPUs without rdmsr/wrmsr instructionsLee Leahy
Quark does not support the rdmsr and wrmsr instructions. In this case use a SOC specific routine to support the setting of the MTRRs. Migrate the code from FSP 1.1 to be x86 CPU common. Since all rdmsr/wrmsr accesses are being converted, fix the build failure for quark in lib/reg_script.c. Move the soc_msr_x routines and their depencies from romstage/mtrr.c to reg_access.c. TEST=Build and run on Galileo Gen2 Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15839 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19soc/intel/common: Add reset_prepare() for common resetAndrey Petrov
Some Intel SoC may need preparation before reset can be properly handled. Add callback that chip/soc code can implement. BUG=chrome-os-partner:55055 Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15soc/intel/common: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I40560b2a65a0cff6808ccdec80e0339786bf8908 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15668 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-01skylake: Generate ACPI timing values for I2C devicesDuncan Laurie
Have the Skylake SOC generate ACPI timing values for the enabled I2C controllers instead of passing it in the DSDT with static timings. The timing values are generated from the controller clock speed and are more accurate than the hardcoded values that were in the ASL which were originally copied from Broadwell where the controller is running at a different clock speed... Additionally it is now possible for a board to override the values using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then the kernel will generate its own timing using the same forumla, but if the SDA hold time value is zero the kernel will NOT generate a correct value and the SDA hold time may be incorrect. This was tested on the Chell platform to ensure all the I2C devices on the board are still operational with these new timing values. Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01soc/intel/common: use nvs.h include for nhlt codeAaron Durbin
The nvs.h header is the one which defines global_nvs_t proper. Don't rely on an indirect inclusion. Change-Id: I89d6a73f65e408c73f068b4a35b5efd361a6e5d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15503 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29soc/intel/{common,skylake}: provide common NHLT SoC supportAaron Durbin
The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() functions should be able to be leveraged on all Intel SoCs which support NHLT. Therefore provide that functionality and make skylake use it. Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-22soc/intel/common/acpi: Add _PTS, _WAK methodsHannah Williams
Change-Id: I72f894fd14bf0e333d9fda970397a3c82de598c3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15121 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21lpss_i2c: Set SDA hold and support custom speed configDuncan Laurie
This I2C controller has separate registers for different speeds to set specific timing for SCL high and low times, and then a single register to configure the SDA hold time. For the most part these values can be generated based on the freq of the controller clock, which is SOC-specific. The existing driver was generating SCL HCNT/LCNT values, but not the SDA hold time so that is added. Additionally a board may need custom values as the exact timing can depend on trace lengths and the number of devices on the I2C bus. This is a two-part customizaton, the first is to set the values for desired speed for use within firmware, and the second is to provide those values in ACPI for the OS driver to consume. And finally, recent upstream changes to the designware i2c driver in the Linux kernel now support passing custom timing values for high speed and fast-plus speed, so these are now supported as well. Since these custom speed configs will come from devicetree a macro is added to simplify the description: register "i2c[4].speed_config" = "{ LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30), LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30), LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30), LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30), }" Which will result in the following speed config in \_SB.PCI0.I2C4: Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) Name (FPCN, Package () { 52, 120, 30 }) Name (HSCN, Package () { 38, 90, 30 }) Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15163 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20soc/intel/common: Add _OSC methodHannah Williams
Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15021 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12soc/intel/common: don't infinitely recurse in busmaster_disable_on_bus()Aaron Durbin
If a bridge has the primary bus equal to the secondary bus the busmaster_disable_on_bus() will infinitely call itself. Avoid the inifinite recursion by checking current bus number against the secondary bus number. BUG=chrome-os-partner:54262 TEST=Ran on reef. Able to actually get the chipset to assert SLP_Sx signals which means no more infinite recursion. Change-Id: I52b21fbba24e6a652ea8f9f87f5f49f60109c8f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15157 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-09soc/intel/common: Add LPSS I2C driverDuncan Laurie
Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys DesignWare I2C block and have a similar configuration of that block. This driver is ported from the Chromium depthcharge project where it was ported from U-Boot originally, though it looks very different now. From depthcharge it has been modified to fit into the coreboot I2C driver model with platform_i2c_transfer() and use coreboot semantics throughout including the stopwatch API for timeouts. In order for this shared driver to work the SOC must: 1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock speed that the I2C controller core is running at. 2) Define the lpss_i2c_base_address() function to return the base address for the specified bus. This could be either done by looking up the PCI device or a static table if the controllers are not PCI devices and just have a static base address. The driver is usable in verstage/romstage/ramstage, though it does require early initialization of the controller to set a temporary base address if it is used outside of ramstage. This has been tested on Broadwell and Skylake SOCs in both pre-RAM and ramstage environments by reading and writing both single bytes across multiple segments as well as large blocks of data at once and with different configured bus speeds. While it does need specific configuration for each SOC this driver should be able to work on all Intel SOCs currently in src/soc/intel. Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15101 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08soc/intel/common: Add common code for acpi c/p/t-state entriesHannah Williams
Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25soc/intel/common: Add common smihandler codeHannah Williams
Provide default handler for some SMI events. Provide the framework for extracting data from SMM Save State area for processors with SMM revision 30100 and 30101. The SOC specific code should initialize southbridge_smi with event handlers. For SMM Save state handling, SOC code should implement get_smm_save_state_ops which initializes the SOC specific ops for SMM Save State handling. Change-Id: I0aefb6dbb2b1cac5961f9e43f4752b5929235df3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18soc/intel/common: Add IGD OpRegion supportAndrey Petrov
Add helper function that fills OpRegion structure based on VBT file content and some reasonable defaults. Change-Id: I9aa8862878cc016a9a684c844ceab390734f3e84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18soc/intel/common: Add utility to load VBT fileAndrey Petrov
Change-Id: I8d3d47ca2fc1fc4c10e61c04b941b6378b9c0f80 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14815 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-12soc/intel/common/mrc_cache: Don't assume FMAP is tied to CHROMEOSAlexandru Gagniuc
The old code only checked for an RW_MRC_CACHE region when CONFIG_CHROMEOS was selected. This assumption is not necessarily true, as one can have FMAP without a CHROMEOS build. As a result, always search FMAP first before falling back on CBFS for locating the MRC cache region. The old logic where CHROMEOS builds would fail when RW_MRC_CACHE was not found is preserved, such that behavior does not change. Change-Id: I3596ef3235eff661af055968ea641f3e9671cdcd Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14757 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-10intel/common/mma: override SAGV to fixed high for MMA testsPratik Prajapati
Set SAGV to 2 (Fixed High) so that MMA test would stress memory at high freq point. MMA tests does not support stressing memory at both high and low points. BRANCH=glados BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu and ran MMA tests. Change-Id: I0b2f6cf9955076f6146b957c4d40fe24e6c3f0e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b16b756d9a74c9111c78fce848b059daee65669 Original-Change-Id: I4c4a59407844e1986fa2cf3a0035aff1d8529cf9 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339002 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-(cherry picked from commit c43d9880fe4efd1e1bb853d35140424fb7dd7e99) Original-Reviewed-on: https://chromium-review.googlesource.com/338847 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/14697 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10util/mma: changing BOOT_STUB to COREBOOT region and few more thingsPratik Prajapati
(1) Added following new function. cbfs_locate_file_in_region - to locate (and mmap) a file in a flash region This function is used to look for MMA blobs in "COREBOOT" cbfs region (2) mma_setup_test.sh would write to "COREBOOT" region. (3) changes in mma_automated_test.sh. Few MMA tests need system to be COLD rebooted before test can start. mma_automated_test.sh would do COLD reboot after each test, and so i would sync the filesystem before doing COLD reboot. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB4). Able to locate MMA files in CBFS Not tested on Glados. Change-Id: I8338a46d8591d16183e51917782f052fa78c4167 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1e418dfffd8a7fe590f9db771d2f0b01a44afbb4 Original-Change-Id: I402f84f5c46720710704dfd32b9319c73c412e47 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331682 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/14125 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-04soc/intel/common/mrc_cache: Honor MRC data as a constant pointerAlexandru Gagniuc
The MRC cache API has absolutely no reason to modify the data it is asked to stash. Reflect that by taking all "data" parameters as const void *. Change-Id: I7a14ffd7d5726aa9aa5db81df82c06e7f87b9d9f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14250 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-04-13src/soc/intel/common: Fix CID 1295499, remove dead codeLee Leahy
Restructure the nvm_is_write_protected routine to eliminate the dead code error. TEST=Build and run on Kunimitsu Change-Id: Ia9170e27d4be3a34760555c48c1635c16f06e6a3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-08soc/intel/common/nvm: Allow overriding to_flash_offset() functionAlexandru Gagniuc
On apollolake, the flash is memory-mapped differently, and the default MMIO to flash calculation does not produce correct results. While the long-term solution is to rewrite the NVM functionality to keep the flash offset as part of its context, as a temporary measure, allow overriding the to_flash_offset() function by declaring it weak. Change-Id: Ic54baeba2441a08cfe1a47e235747797f6efb59b Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14247 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-02soc/intel/common: Use SoC specific routine to read/write MTRRsLee Leahy
The registers associated with the MTRRs for Quark are referenced through a port on the host bridge. Support the standard configurations by providing a weak routines which just do a rdmsr/wrmsr. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The MTRRs are displayed and * The message "FspTempRamExit returned successfully" is displayed TEST=Build and run on Galileo Change-Id: If2fea66d4b054be4555f5f172ea5945620648325 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13529 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-01-22soc/braswell: Add method for Wifi regulatory domainFelix Durairaj
Get the WRDD domain code from VPD and put it in global nvs. WRDD method in wifi.asl returns this value from global nvs. This wifi.asl should be included in dsdt.asl under the root port where wifi module resides. Original-Reviewed-on: https://chromium-review.googlesource.com/314373 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Change-Id: I809d28f10e80681471a785e604df102fb943a983 Signed-off-by: fdurairx <felixx.durairaj@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-11mrc_cache: add version fieldAaron Durbin
In order to allow for updateable memory init code on intel x86 platforms one needs to ensure the saved mrc data matches the code consuming the data. To that end add a version field to the saved data structure. BUG=chrome-os-partner:46050 BRANCH=None TEST=Built and booted on glados. Suspended and resumed. Also verified version mismatch path. Change-Id: Ie86db1750af5d9bff6446999b0d04b60612f8d29 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12700 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08soc/intel/common: Remove USE_FMAP - symbol doesn't existMartin Roth
The USE_FMAP Kconfig symbol doesn't exist, so remove things that are depending on it not being enabled. Change-Id: I1946f5d13a762ab07744a1d9a6cb754433e6701d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-27soc/intel/common: Fix whitespace in KconfigMartin Roth
Change leading spaces to tabs. Change-Id: Ief138f5f68198578ba9dddb8fbdabbd9a0185a21 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-20intel: Add MMA feature in corebootPratik Prajapati
This patch implements Memory Margin Analysis feature in coreboot. Few things to note (1) the feature is enabled by setting CONFIG_MMA=y in the config file (2) coreboot reads mma_test_metadata.bin from cbfs during romstage and gets the name of MMA test name and test config name. Then coreboot finds these files in CBFS. If found, coreboot passes location and size of these files to FSP via UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test would be executed during memory init. (3) FSP passes MMA results data in HOB and coreboot saves it in cbmem (4) when system boots to OS after test is executed cbmem tool is used to grab the MMA results data. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests Not tested on Glados CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7 Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299476 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12481 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-27FSP 1.1: Move common FSP codeLee Leahy
Move the FSP common code from the src/soc/intel/common directory into the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values associated with this common code. BRANCH=none BUG=None TEST=Build and run on kunimitsu Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440 Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306350 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12156 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-10-27fsp/intel common: Add support for Gfx PEIM (AKA GOP)robbie zhang
This patch provides the lb_framebuffer() for coreboot table with fsp gop usage, add Igd Opregion register defines, and update the UPD naming following fsp. BRANCH=none BUG=chrome-os-partner:44559 TEST=Built and boot on kunimitsu/glados. Change-Id: I9cf9d991eb09d698e7a78323cd855c4c99b55eca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd6834057cca60716bc0e24cfc2cd60fed02be7a Original-Change-Id: I64987e393c39a7cc1084edf59e7ca51b8c5ea743 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303539 Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR, we also remove the _MSR suffix, as they are, by definition, MSRs. Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-11skylake: add support for verstageAaron Durbin
The right files just need to be added to the verstage build. Do that so a stand alone verstage builds and links. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I2d0c98760494e2f4657ee35b6f155690939d2d18 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11827 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11soc/intel/common: use prog_locate() for finding fsp.binAaron Durbin
The current method was only taking the cbfs path. Because of this fsp.bin was never being utilized from the RW slots. Using prog_locate() now provides both the cbfs and vboot locate methods for free. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I2b3e088326d5a965ad90806a7950b9f401ed57de Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11831 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-11intel fsp1_1: prepare for romstage vboot verification splitAaron Durbin
In order to introduce a verstage which performs vboot verification the cache-as-ram environment needs to be generalized and split into pieces that can be utilized in romstage and/or verstage. Therefore, the romstage pieces were removed from the cache-as-ram specific pieces that are generic: - Add fsp/car.h to house the declarations for functions in the cache-as-ram environment - Only have cache_as_ram_params which are isolated form the cache-as-ram environment aside from FSP_INFO_HEADER. - Hardware requirements for console initialization is done in the cache-as-ram specific files. - Provide after_raminit.S which can be included from a romstage separated from cache-as-ram as well as one that is tightly coupled to the cache-as-ram environment. - Update the fallout from the API changes in soc/intel/{braswell,common,skylake}. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302481 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11816 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11soc/intel/common: remove chipset specific callsAaron Durbin
The report_platform_info() and set_max_freq() are not being used similarly on skylake and braswell. With the addition of other SoCs I suspect a similar pattern will emerge. Instead of having weak functions to ensure things link with the hardcoded policy push these calls into their respective SoC homes. For parity, both skylake and braswell were updated to be consistent with the same calls prior to this patch. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Built braswell. Original-Change-Id: I3371d09aff0629503254296955fef28d35754a38 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/303334 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2de33632ed127cac52d7075cbad95cd6387a1b46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11815 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11intel SOC common: Remove unused parametersLee Leahy
Eliminate unused parameters from the console initialization. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Original-Change-Id: Iacacea292d43615e9d2f8e5d3ec67e77f3f08906 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/301204 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: I3a0ea948ce106b07cb6aa872375ce588317dc437 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11814 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11Braswell: Modify CB to accomodate new FSPv83Subrata Banik
Latest FSPv83 made some change related to UPD/VPD need this patch to align those BUG=None TEST=Build and Boot Cyan System BRANCH=strago-7287.B CQ-DEPEND=CL:*226897 Original-Change-Id: I6395f3a1f4eecaef14fc4720b00252f9e6143fa3 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291394 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303137 Original-Commit-Ready: John Zhao <john.zhao@intel.com> Original-Tested-by: John Zhao <john.zhao@intel.com> Change-Id: I9920eea84b802699454850bfde489668201ffeb6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11813 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11intel: update common and FSP cache-as-ram parametersAaron Durbin
Instead of just passing bits, tsc_low, tsc_high, and an opaque pointer to chipset context those fields are bundled into a cache_as_ram_params struct. Additionally, a new struct fsp_car_context is created to hold the FSP information. These could be combined as the existing romstage code assumes what the chipset_context values are, but I'm leaving the concept of "common" alone for the time being. While working in that area the ABI between assembly and C code has changed to just pass a single pointer to cache_as_ram_params struct. Lastly, validate the bootloader cache-as-ram region with the Kconfig options. BUG=chrome-os-partner:44676 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Ib2a0e38477ef7c15cff1836836cfb55e5dc8a58e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/300190 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Change-Id: Ic5a0daa4e2fe5eda0c4d2a45d86baf14ff7b2c6c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11809 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-07cbfs: add struct cbfsfAaron Durbin
Now that cbfs is adding more metadata in the cbfs file header one needs to access that metadata. Therefore, add struct cbfsf which tracks the metadata and data of the file separately. Note that stage and payload metadata specific to itself is still contained within the 'data' portion of a cbfs file. Update the cbfs API to use struct cbfsf. Additionally, remove struct cbfsd as there's nothing else associated with a cbfs region aside from offset and size which tracked by a region_device (thanks, CBFS_ALIGNMENT!). BUG=None BRANCH=None TEST=Built and booted through end of ramstage on qemu armv7. Built and booted glados using Chrome OS. Change-Id: I05486c6cf6cfcafa5c64b36324833b2374f763c2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17intel/common: Add common code for filling out ACPI _SWSDuncan Laurie
Add common code for filling out the NVS fields that are used by the ACPI _SWS methods. The SOC must provide a function to fill out the wake source data since the specific data inputs vary by platform. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I4f3511adcc89a9be5d97a7442055c227a38c5f42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cee5fa176c16ca44712bce8f3c8045daa5f07339 Original-Change-Id: I16f446ef67777acb57223a84d38062be9f43fcb9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298167 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11646 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-10fsp1_1: provide binding to UEFI versionAaron Durbin
FSP has some unique attributes which makes integration cumbersome: 1. FSP header files do not include the types they need. Like EDKII development it's expected types are provided by the build system. Therefore, one needs to include the proper files to avoid compilation issues. 2. An implementation of FSP for a chipset may use different versions of the UEFI PI spec implementation. EDKII is a proxy for all of UEFI specifications. In order to provide flexibility one needs to binding a set of types and structures from an UEFI PI implementation. 3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h file which defines it's own types. Commonality between FSP chipset implementations are only named typedef structs. The fields within are not consistent. And because of FSP's insistence on typedefs it makes it near impossible to forward declare structs. The above 3 means one needs to include the correct UEFI type bindings when working with FSP. The current implementation had the SoC picking include paths in the edk2 directory and using a bare <uefi_types.h> include. Also, with the prior fsp_util.h implementation the SoC's FSP FspUpdVpd.h header file was required since for providing all the types at once (Generic FSP 1.1 and SoC types). The binding has been changed in the following manner: 1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1 selects. No other bindings are currently available, but this provides the policy. 2. Based on CONFIG_UEFI_2_4_BINDING the proper include paths are added to the CPPFLAGS_common. 3. SoC Makefile.inc does not bind UEFI types nor does it adjust CPPFLAGS_common in any way. 4. Provide a include/fsp directory under fsp1_1 and expose src/drivers/intel/fsp1_1/include in the include path. This split can allow a version 2, for example, FSP to provide its own include files. Yes, that means there needs to be consistency in APIs, however that's not this patch. 5. Provide a way for code to differentiate the FSP spec types (fsp/api.h) from the chipset FSP types (fsp/soc_binding.h). This allows for code re-use that doesn't need the chipset types to be defined such as the FSP relocation code. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted on glados. Signed-off-by: Aaron Durbin <adubin@chromium.org> Change-Id: I894165942cfe36936e186af5221efa810be8bb29 Reviewed-on: http://review.coreboot.org/11606 Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins)
2015-09-10intel/common: Print board ID if enabledDuncan Laurie
Read and print the board ID if it is enabled in the mainboard. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I9d50089242b3a2f461dff2b1039adc8f0347179e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f245854b30c40eda38453c1b0ae5d3b8b18c010f Original-Change-Id: Ifbd7c2666820ea146dc44fbc42bfe201cb227ff6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297756 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11577 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-04bootstate: remove need for #ifdef ENV_RAMSTAGEAaron Durbin
The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however the current state of the header meant bad build errors in non-ramstage. Therefore, people had to #ifdef in the source. Remove that requirement. Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11492 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-29fsp raminit: Add romstage_params to soc_memory_init_paramsDuncan Laurie
The SOC handler for memory init params is only taking UPD as an input which does not allow it to use romstage_params. In addition the UPD input is called params which is confusing so rename it to upd so romstage_params can be passed properly. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2 Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294066 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11413 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29soc/intel/common/fsp_ramstage.c: Don't die when printing HOB infoAlexandru Gagniuc
It doesn't make sense to die() when printing information. In fact the die() are protected by DISPLAY_HOBS config option. This can get confusing, so replace die() calls with printk(). Also since these messages are designed to be informational, keep them at BIOS_INFO log level. Change-Id: Id75b9a54f4aea23074a7489d12809cc2da05f1cd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11456 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29soc/intel/common: Add mrc.cache file to CBFS when appropriateAlexandru Gagniuc
The code in mrc_cache.c doesn't check for the presence of 'mrc.cache', and just returns hardcoded value for he location of he MRC cache. This becomes a problem when there is a CBFS file at the same location, which can get overwritten. A CBFS file is created to cover this region so that nothing can be added there. This has the advantage of creating a build time error if another cbfs file is hardcoded over the same region. The default location of the MRC cache is also moved to 4G - 128K to ensure that it defaults to something within CBFS. Change-Id: Ic029c182f5a2180cb680e09b25165ee303a448a3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-21soc/intel/common: CACHE_MRC_SETTINGS doesn't depend on HAVE_MRCMartin Roth
The FSP platforms use CACHE_MRC_SETTINGS without setting HAVE_MRC, which caused a Kconfig warning. Since CACHE_MRC_SETTINGS doesn't really depend on HAVE_MRC anymore, remove the dependency in Kconfig. Fixes Kconfig warnings: warning: (CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_SETTINGS which has unmet direct dependencies (SOC_INTEL_BROADWELL && HAVE_MRC || SOC_INTEL_COMMON && HAVE_MRC) Change-Id: Id1c108f73d19cbd53b91e1671d57e7752be5d96d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-14intel/common: fix stage_cache_external_region()Aaron Durbin
The stage_cache_external_region() calculation is actually dependennt on the properties of the chipset. The reason is that certain regions within the SMRAM are used for chipset-specific features. Therefore, provide an API for abstracting the querying of subregions within the SMRAM. The 3 subregions introduced are: SMM_SUBREGION_HANDLER - SMM handler area SMM_SUBREGION_CACHE - SMM cache region SMM_SUBREGION_CHIPSET - Chipset specific area. The subregions can be queried using the newly added smm_subregion() function. Now stage_cache_external_region() uses smm_subregion() to query the external stage cache in SMRAM, and this patch also eliminates 2 separate implementations of stage_cache_external_region() between romstage and ramstage. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290833 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14intel/common: use external stage cache for fsp_ramstageAaron Durbin
The fsp_ramstage.c code was not taking advantage of the stage cache which does all the accounting and calculation work for the caller. Remove the open coded logic and use the provided infrastructure. Using said infrastructure means there's no need for the FSP_CACHE_SIZE Kconfig variable. Therefore, remove it. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I4363823c825b4a700205769f109ff9cf0d78b897 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290831 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifd3cc4a538daac687949c5f4cab2c687368d6787 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11196 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14fsp1_1: fsp_relocate: use struct region_device and struct progAaron Durbin
Using struct prog and struct region_device allows for the caller to be none-the-wiser about where FSP gets placed. It also allows for the source location to be abstracted away such that it doesn't require a large mapping up front to do the relocation. Lastly, it allows for simplifying the intel/commmon FSP support in that it can pass around a struct prog. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I034b04ab2b7e9e01f5ee14fcc190f04b90517d30 Original-Signed-off-by: Aaron Durbin <adurbin@chroumium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290830 Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: Ibe1f206a9541902103551afaf212418fcc90e73c Signed-off-by: Aaron Durbin <adurbin@chroumium.org> Reviewed-on: http://review.coreboot.org/11193 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.cAaron Durbin
acpi_is_wakeup_s3() was introduced in upstream coreboot while the FSP support code was written. Move to using that instead of using the romstage_handoff structure directly. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I71601a4be3c981672e25e189c98abb6a676462bf Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290720 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2ae4d9906e0891080481fb58b941921922a989d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-13soc/common/intel: Reset is not dependend upon FSPLee Leahy
Remove dependency of common reset code on FSP BRANCH=none BUG=None TEST=Build and run on Braswell and Skylake Original-Change-Id: I00052f29326f691b6d56d2349f99815cafff5848 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286932 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7f59f0aad7dfae92df28cf20fff2d5a684795d22 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: http://review.coreboot.org/11165 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-07-23intel: common: Let mainboard supplement FSP memory infoDuncan Laurie
Since the FSP memory info HOB does not return all the data that we need about a DIMM add a weak function that will allow the mainboard to supplement the generated memory_info structure. Ideally this would not be necessary but until FSP returns the module part number we need this. BUG=chrome-os-partner:42975, chrome-os-partner:42561 BRANCH=none TEST=run "mosys memory spd print all" on glados Change-Id: Ic6d0ee0a31d23efcf7e7d7f18a74e944e09e7b46 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 34ad7f1906ba526e52d38d5a6bce7b88b83f0c13 Original-Change-Id: I8509c5c627c1605894473fdea567e7f7ede08cf9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286876 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11033 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23intel/common: Add SMBIOS memory widthLee Leahy
Add SMBIOS symbols to define the memory width. Update the Intel common code to display the memory width and provide the memory width to SMBIOS. Also display the memory frequency, size and bus width in decimal. BRANCH=none BUG=None TEST=None Change-Id: I67b814d79fdbbf6ce65ac6b4a8282ab15fb91369 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0e59c7260afd180f3adcbeda7cef1b9eca3ed846 Original-Change-Id: Ibd26812c2aad4deaab62111b1e018be69c4faa7b Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282115 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11032 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21intel/common: remove printk in pre_console_init()rsatapat
printk called before console init causes sluggish execution because of Rx timeout. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp and tested LPSS logs on RVP3 and Kunimitsu. Change-Id: I61d5c0f5a4e93695bcba90b7ac7d4f68e2d625be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 77c58702c8279c6d9c6ae1c946bf1b76df20714d Original-Change-Id: Ib85029456059248cc2c88aaccba4fa12cc5a76be Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284823 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10996 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21intel fsp: remove CHIPSET_RESERVED_MEM_BYTESAaron Durbin
FSP 1.1 platforms should be conforming to the spec. In order to ensure following specification remove the crutch that allows FSP to no conform. BUG=chrome-os-partner:41961 BRANCH=None TEST=Built. Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285187 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21Braswell: Remove GOP from normal boot mode.Abhay Kumar
Removing GOP initialization in normal mode since we don't need to show splash screen in normal mode. GOP will get initialized in dev and recovery mode. BRANCH=none BUG=None TEST=Splash screen will come only in dev or recovery mode. Change-Id: Ia5e12cf45d723f2f14c447e29b78119552d5e1ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 79d1c877343704ea51143b922d9ac9209be4d4b5 Original-Change-Id: Id5ca99757427206413483d07b4f422b4c0abfa5d Original-Signed-off-by: Abhay <abhay.kumar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285300 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10990 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-26soc/intel/common: Restrict common romstage/ramstage code to FSPLee Leahy
Restrict the use of the common romstage/ramstage code to FSP 1.1 BRANCH=none BUG=None TEST=Build and run on cyan/sklrvp Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10653 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25soc/intel/common/Kconfig: Fix warning & whitespaceMartin Roth
Because of a missing close quote, we have the warning: src/soc/intel/common/Kconfig:52:warning:multi-line strings not supported This was added in commit 0946ec37 -Intel Common SOC:Add romstage support The whitespace issue - using spaces instead of a leading tab was added in the same commit. Change-Id: I429c66afb5a7e10ca0e0ef619ac46722c63fb376 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10654 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-06-24Intel/common: Remove copyright addressLee Leahy
Remove the copyright address from the remaining files. BRANCH=none BUG=None TEST=None Change-Id: I026a0ff2bcb6c9580b45700edab446b787223007 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-24Intel Common SOC: Add romstage supportLee Leahy
Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26fmap: new API using region_deviceAaron Durbin
Instead of being pointer based use the region infrastrucutre. Additionally, this removes the need for arch-specific compilation paths. The users of the new API can use the region APIs to memory map or read the region provided by the new fmap API. Change-Id: Ie36e9ff9cb554234ec394b921f029eeed6845aee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-30kbuild: Don't require intel/common changes for every socStefan Reinauer
In the true spirit of separating components more strictly and allowing to add new components to coreboot without touching existing code, move Intel common code selection to the soc Kconfig and out of src/soc/intel/common/Makefile.inc Change-Id: I0a70656bb9f4550b6088e9f45e68b5106c0eb9af Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10031 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-29kbuild: automatically include SOCsStefan Reinauer
This change switches all SOC vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in soc/Makefile.inc or in soc/<vendor>/Makefile.inc. This means, vendor and SOC directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9799 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-18soc/intel/common: Add common reset codeLee Leahy
Move reset support into the Intel common branch. Prevent breaking of existing platforms by using a Kconfig value to select use of the common reset code. BRANCH=none BUG=None TEST=Build and run on Glados Change-Id: I5ba86ef585dde3ef4ecdcc198ab615b5c056d985 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 85d8a6d9628a66cc8d73176d460cd6c5bf6bd6b2 Original-Change-Id: I5048ccf3eb593d59301ad8e808c4e281b9a0aa98 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/248301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9505 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-18soc/intel/common: Add function to protect MRC cacheDuncan Laurie
Add support for applying write protection to the MRC cache region in SPI flash. This is only enabled if there is write protect GPIO that is set, and the flash status register reports that the flash chip is currently write protected. Then it will call out to a SOC specific function that will enable write protection on the RW_MRC_CACHE region of flash. The implementation is not quite as clean as I would like because there is not a common flash protect interface across SOCs so instead it relies on a new Kconfig variable to be set that will indicate a SOC implements the function to protect a region of SPI flash. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus 1) with either WPSW=0 or SRP0=0 the PRR is not applied 2) with both WPSW=1 and SRP0=1 the PRR is applied Change-Id: If5907b7ddf3f966c546ae32dc99aa815beb27587 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a3e0e71dfd7339aab171a26b67aec465a3f332d6 Original-Change-Id: I94e54e4723b1dcdacbb6a05f047d0c0ebc7d8711 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241170 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-06baytrail: Fix hdmi audio choppy issueKein Yuan
Disable VC setting for HDA so hdmi audio choppy issue will be eliminated. Change HDA initialize steps to sync with UEFI reference code. BUG=chrome-os-partner:25651 BRANCH=Baytrail TEST=Does not have choppy noise during video playing Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com> Original-Change-Id: I45d49123d369b7d075776215e709af5801ea696d Original-Reviewed-on: https://chromium-review.googlesource.com/186024 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Tested-by: Benson Leung <bleung@chromium.org> Original-Commit-Queue: Bernie Thompson <bhthompson@chromium.org> (cherry picked from commit 9f725a40f77cd684b2e230bd226d78d87b56e73b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4fc10a161e5996e14d4823491fb62a7beff39bcc Reviewed-on: http://review.coreboot.org/9297 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-01-06Revert "Re-factor 'to_flash_offset()' into 'spi_flash.h'"Kyösti Mälkki
This reverts commit 9270553fff23462fcb298f154296319bf3639d15. Change-Id: I195f721ce7a18aac6c1aa6f4e0f9284455d531b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8138 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06doxygen fixes: change @var to @param varMartin Roth
These files were trying to document the parameters, but didn't have the syntax quite right. Change the comments from @varname to @param varname as required by doxygen. Change-Id: I63662094d3f1686e3e35b61925b580eb06e72e28 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8100 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06Re-factor 'to_flash_offset()' into 'spi_flash.h'Edward O'Callaghan
Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by Clang complaining that the function 'to_flash_offset' is unused. Change-Id: Ic75fd2fb4edc5e434c199ebd10c7384d197e0c63 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-22baytrail: Move HDA verb table to Intel SOC common directoryDuncan Laurie
This is common code for Intel SOC that can be shared. Change-Id: Ic703f36f56a8238d5cc1248b353d8c3a49827a9a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3a9057b9616c54a8404eee55511743d2492dbc28) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6968 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-15 18:15:21 +0000