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Since there are multiple controllers in the LPSS and all use the same
frequency, provide a single Kconfig option for LPSS_CLOCK_MHZ.
BUG=b:35583330
Change-Id: I3c0cb62d56916e6e5f671fb5f40210f4cb33316f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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When using rise_time_ns and fall_time_ns there's currently not
a way to specify a target data hold time. The internal 300ns
value is used. However, that isn't always sufficient depending on
bus topology. Therefore, provide the ability to specify data
hold time in ns from devicetree, defaulting to default value if
none are specified.
BUG=b:36469182
Change-Id: I86de095186ee396099709cc8a97240bd2f9722c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19064
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fix the following warning detected by checkpatach.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build and run on Galileo Gen2
Change-Id: Ic266c077eb115e0c7d934c15bcc4cc9b9e530a39
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18756
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The wrong value was used for reporting an error when a requested
bus speed was made that isn't supported. Use the requested value.
Change-Id: I6c92ede3d95590d95a42b40422bab88ea9ae72a1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17474
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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If the SoC clock speed is not supported there is supposed to
be an error printed. However, the value printed was wrong which
was dereferencing a NULL struct. Fix that.
Change-Id: I5021ad8c1581d1935b39875ffa3aa00b594c537a
Found-by: Coverity Scan #1365977
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17468
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The default register count calculations are leading to higher
frequencies than expected. Provide an alternative method for
calculating the register counts by utilizing the rise and
fall times of the bus. If the rise time is supplied the
rise/fall time values are used, but the register overrides
take precedence over the rise/fall time calculation. This
allows platforms to choose whichever method works the best.
BUG=chrome-os-partner:58889
Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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The apollolake and skylake had duplicate stanzas of code for
initializing the i2c buses. Additionally, they also had very
similar structures for providing settings for the i2c speed
control. Introduce a new struct lpss_i2c_bus_config and
utilize it in both apollolake and skylake thereby removing
the need for SoC-specific structres. The new structure is
used for initializing a bus fully as the lpss i2c API is
simplified in that lpss_i2c_init() is only required to be
called. The struct lpss_i2c_bus_config structure is passed
in for both initializing and filling in the SSDT information.
The formerly exposed functions are made static to reduce the
external API exposure.
BUG=chrome-os-partner:58889
Change-Id: Ib4fa8a7a4de052da75c778a7658741a5a8e0e6b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17348
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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When doing long transcations on an I2C bus at standard speed we saw
that long transactions could go over the 4ms limit while waiting for
it to complete on the bus.
Increase this so we can use standard speed for testing and debug in
firmware. (as there is no way to force standard speed in the kernel)
BUG=chrome-os-partner:58666
TEST=boot eve board with cr50 TPM and I2C bus at 100khz
Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17213
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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It is very useful to have the ability to see I2C transactions
performed by the host firmware. This patch adds a simple
Kconfig option that will enable debug output.
Change-Id: I55f1ff273290e2f4fbfaea56091b2df3fc49fe61
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16590
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This change modifies the lpss_i2c driver to behave more like
the Linux kernel driver. In particular the controller is only
enabled when processing a transaction, and is disabled after.
This means that errors in one transaction will not affect later
transactions.
Also when disabling the controller the code is supposed to wait
on the enable bit in the "enable status" register and not in
the enable control register. In order to get access to this
register the reg map was expanded to include all registers.
This was tested with the cr50 TPM driver to ensure that if a
transaction does fail that it can be successfully retried instead
of the bus being unusable.
Change-Id: I43a546d54996ba0f08550a801927b8f7a6690cda
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16589
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Increase the default timeout in the LPSS I2C driver to 4ms
from 2ms. During testing with some slower devices I found
that the existing timeout could be too short leading to
transaction failures.
Change-Id: Ied86c7a0aa26d55b31f447c5938803c194d0045e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16392
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Have the Skylake SOC generate ACPI timing values for the enabled I2C
controllers instead of passing it in the DSDT with static timings.
The timing values are generated from the controller clock speed and
are more accurate than the hardcoded values that were in the ASL which
were originally copied from Broadwell where the controller is running
at a different clock speed...
Additionally it is now possible for a board to override the values
using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then
the kernel will generate its own timing using the same forumla, but if
the SDA hold time value is zero the kernel will NOT generate a correct
value and the SDA hold time may be incorrect.
This was tested on the Chell platform to ensure all the I2C devices on
the board are still operational with these new timing values.
Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys
DesignWare I2C block and have a similar configuration of that block.
This driver is ported from the Chromium depthcharge project where it
was ported from U-Boot originally, though it looks very different now.
From depthcharge it has been modified to fit into the coreboot I2C
driver model with platform_i2c_transfer() and use coreboot semantics
throughout including the stopwatch API for timeouts.
In order for this shared driver to work the SOC must:
1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock
speed that the I2C controller core is running at.
2) Define the lpss_i2c_base_address() function to return the base
address for the specified bus. This could be either done by looking
up the PCI device or a static table if the controllers are not PCI
devices and just have a static base address.
The driver is usable in verstage/romstage/ramstage, though it does
require early initialization of the controller to set a temporary base
address if it is used outside of ramstage.
This has been tested on Broadwell and Skylake SOCs in both pre-RAM and
ramstage environments by reading and writing both single bytes across
multiple segments as well as large blocks of data at once and with
different configured bus speeds.
While it does need specific configuration for each SOC this driver
should be able to work on all Intel SOCs currently in src/soc/intel.
Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15101
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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