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2018-06-02soc/intel/common: Add edge trigger configuartion for IOAPIC IRQ modeAamir Bohra
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/26730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-05-27soc/intel/cannonlake: Select common XHCI codeSubrata Banik
This patch select CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI to include common xhci code block. BUG=b:78109109 BRANCH=none TEST=Build and boot cnlrvp Change-Id: I7f1e59792159dae5835fbbe7fcb1604fc01893ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-18soc/intel: Add support for USB ACPI code generationDuncan Laurie
To support generating USB devices in ACPI the platform needs to know how to determine a device name for each USB port, and for any root hubs that may be present. Recent Intel platforms route all ports to an XHCI controller through a root hub. This is supported by considering the root hub to be USB port type 0, the USB 2.0 ports to be type 2, and the USB 3.0 ports to be type 3. This was tested with a Kaby Lake platform by adding entries to the devicetree and checking the resulting SSDT. Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-14soc/intel/denverton_ns: port gpio to intelblockJulien Viard de Galbert
The intelblock code is common code already used by appololake and cannonlake platform. The denverton platform also use a similar gpio controller so the intelblock code can be used as well. Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24928 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14cpu/x86: Add support to run function with argument over APsSubrata Banik
This patch ensures that user can pass a function with given argument list to execute over APs. BUG=b:74436746 BRANCH=none TEST=Able to run functions over APs with argument. Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-05soc/intel: Add KBL-R pci id supportLijian Zhao
Add KBL-R internal graphics device pci ids into coreboot. BUG=N/A TEST=Boot up fine on kabylake-r platform with display on. Change-Id: I0813247624770b70fe8b3ec3825fd17a9878cd0e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/26018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@chromium.org>
2018-04-27soc/intel/common/block/xdci: Use vboot_can_enable_udc in xdci_can_enableFurquan Shaikh
This change uses the newly added vboot_can_enable_udc to decide if it is okay to enable xDCI in vboot developer mode. BUG=b:78577893 BRANCH=poppy Change-Id: Ia83b91ce17eec782faf5bb318ad8c00c09e2db05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-25soc/intel/common: disable paging if PAGING_IN_CACHE_AS_RAM enabledAaron Durbin
When tearing down cache-as-ram disable paging if PAGING_IN_CACHE_AS_RAM is enabled. BUG=b:72728953 Change-Id: I86e8a57a1187876dcbedce9f4f6b05be30aea7c6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23cpu/x86: move NXE and PAT accesses to paging moduleAaron Durbin
The EFER and PAT MSRs are x86 architecturally defined. Therefore, move the macro defintions to msr.h. Add 'paging' prefix to the PAT and NXE pae/paging functions to namespace things a little better. BUG=b:72728953 Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20soc/intel/common: Adjust LPC Generic IO setupLijian Zhao
Check same IO ranges get programmed first, if so just skip it to avoid double programming. BUG=b:77944335 TEST=Boot up with mewoth board, and check serial log, there's no error message about "LPC: Cannot Open IO Window: ". Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25667 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11soc/intel/common/block/cpu: Fix cpu_get_power_maxMario Scheithauer
To avoid rounding errors with the current data types, the formula in this function must be converted. Change-Id: I75d05165fd9e5a0992330df00f8665a05d2daeb3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11soc/intel/common/block/gspi: Set Clock Update Bit for clock updates.Shamile Khan
This is required for clock parameter settings to take effect. BUG=b:75306520 BRANCH=None TEST=On Octopus, used a scope to check that spi_clk fed to tpm is 1 MHz Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11soc/intel: Remove superfluous pointers variablesArthur Heymans
Change-Id: I639be58df358129c1f420cf8d1540edd408859a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11soc/intel/common: Configure all possible GFX DSM memory reserve rangeSubrata Banik
Intel internal graphics preallocated memory size should be selected from below lists as per Intel FSP UPD header: 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB This patch ensures that coreboot can report the same preallocated memory range for intel grapics during memory layout calculation. Note: Today all existing SoCs(except Cannonlake) are supported under intel common code block design may not need to use any other values than 0x0-0x05 for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for early SoC samples and validation requirement. This code block to justify all differnet possible ranges that FSP may support for a platform. TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB and coreboot could able to calculate GFX DSM range accordingly. Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-10soc/intel/common: prepare for lpss clock splitAaron Durbin
Apparently Intel had decided to use different clock speeds for some of its IP blocks in some of its designs. The i2c designware driver has already been moved into common code allowing for its own Kconfig value. That currently leaves SPI (UART isn't using the clock currently). Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock speeds present in the system for the various IP blocks. BUG=b:75306520 Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25608 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09soc/intel/common: Add funtion to modify PAT & NXE bitNaresh G Solanki
Add function to modify NXE bit & PAT. BUG=None BRANCH=None TEST=Make sure build for Glkrvp is successful. Change-Id: I265d6d5ca538496934a375eb8d99d52879522051 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25480 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28soc/intel/common/block: add VMX supportMatt DeVillier
Enable VMX if supported by CPU and enabled in board devicetree. Check lock bit unset before enabling VMX. Change-Id: Ic57eac45e9c65baa4479735c6d70a7eb685f080e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-28soc/intel/common: Add function to check if xDCI is allowedDuncan Laurie
When CONFIG_VBOOT is enabled then the xDCI controller should only be enabled if the system is in developer mode. This prevents a system in normal/verified mode from being used as a USB peripheral device which could potentially be used to access user data. This change adds a function to return whether xDCI can be enabled or not, which will be used by the SOCs. Change-Id: Ie3ee9dd7077c094a01fd857a2e4033a12ce8979b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-26soc/intel: Add KBL-S MCH and some KBL PCH supportGaggery Tsai
This patch adds the support for KBL-S MCH and Z270, H270, B250 and Q250 PCH chips. BUG=None BRANCH=None TEST=Boot with KBL-S CPU and B250/H270 PCHs. Change-Id: If03abb215f225d648505e05274e2f08ff02cebdc Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/25305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-03-09soc/intel/common: Enable decoding of the COMB range to LPC based on KconfigSubrata Banik
By default all Intel platform has enable IO decode range for COMA if CONFIG_DRIVERS_UART_8250IO is selected. With this patch, COMB will get enable based on CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE Kconfig selection. Also make lpc_enable_fixed_io_ranges() function returns Enabled I/O bits to avoid an additional pci configuration read to get the same data. Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-03-08soc/intel/common/block/gspi: set cs polarity before usingNick Vaccaro
Move call to __gspi_cs_change() in gspi_ctrlr_setup() to after initialization of cs polarity since it requires polarity to be set to work properly. Failure to do so confuses cr50. BUG=b:70628116 BRANCH=chromeos-2016.05 TEST='emerge-meowth coreboot' and verify on scope that chip select polarity is correct for the first transaction. Change-Id: I20b4f584663477d751a07889bccc865efbf9c469 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/25013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-06soc/intel: Fix MCFG end bus numberDuncan Laurie
The ACPI MCFG table is generated with a static end bus number of 255, which expects that the reserved range in E820 is 256MB. However the actual MCFG range is configurable with Kconfig, so these two values may not match when the OS tries to determine the range: PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) PCI: MMCONFIG 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) (size reduced!) acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge Instead of forcing the end bus number to be 255 use the Kconfig value to set it based on the current configuration. Tested on a fizz device to ensure that the kernel no longer complains: PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24974 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-05soc/intel/common/block/smm: Add configurable delay before entering S5Furquan Shaikh
This change adds a configurable delay in milliseconds before SLP_EN is set in SLP_SMI for S5. Reason for doing this is to avoid race between SLP and power button SMIs. On some platforms (Nami, Nautilus), it was observed that power button SMI triggered by EC was competing with the SLP SMI triggered by keyboard driver. Keyboard driver indicated power button press which resulted in depthcharge triggering SLP_SMI, causing the AP to enter S5. However, the power button press also causes the EC to send a pulse on PWRBTN# line, which is debounced for 16ms before an interrupt is triggered. This interrupt was generated after SLP_SMI is processed which resulted in the device waking back up from S5. This change adds a config option SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is used to add a delay before SLP_EN is set for S5. This change should only affect CHROMEOS boards as the config option will be 0 in other cases. BUG=b:74083107 TEST=Verified that nami, nautilus do not wake back from S5 on power button press at dev mode screen. Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22soc/intel/common/block/smm: Add option to have SOC specific SMI Handler at ↵Subrata Banik
finalize() This patch ensures common code provides an option to register a SOC specific SMI handler before booting to OS (specifically during ramstage). Change-Id: I50fb154cc1ad4b3459bc352d2065f2c582711c20 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tung Lun Loo <tung.lun.loo@intel.com>
2018-02-22soc/intel/common/block/pcr: Add function for executing PCH SBI messageSubrata Banik
This function performs SBI communication Input: * PID: Port ID of the SBI message * Offset: Register offset of the SBI message * Opcode: Opcode * Posted: Posted message * Fast_Byte_Enable: First Byte Enable * BAR: base address * FID: Function ID * Data: Read/Write Data * Response: Response Output: * 0: SBI message is successfully completed * -1: SBI message failure Change-Id: I4e49311564e20cedbfabaaceaf5f72c480e5ea26 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23809 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-20src/soc: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-16soc/intel/common/block/gpio: Change group offset calculationBora Guvendik
Add group information for each gpio community and use it to calculate offset of a pad within its group. Original implementation assumed that the number of gpios in each group is same but that lead to a bug for cnl since numbers differ for each group. BUG=b:69616750 TEST=Need to test again on SKL,CNL,APL,GLK Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22571 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07soc/intel/common/block: Fix SATA chipset register definitions anomaliesSubrata Banik
SATA PCH configuration space registers bit mapping is different for various SOCs hence common API between SPT-PCH and CNL-PCH causing issue. Add new Kconfig option to address this delta between different PCH. Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCESBarnali Sarkar
This patch changes the sequence of post_cpus_init() function of mp_init to very last of the stages, i.e., ON_EXIT of BS_WRITE_TABLES for normal boot path, and to ON_ENTRY of BS_OS_RESUME for S3 Resume path. Also, the fast_spi_cache_bios_region() call inside post_cpus_init() function is left out, since caching the SPI Bios region is not required now at this stage. BUG=none BRANCH=none TEST=Build and boot in Soraka (KBL), executed stability tests on multiple systems. Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/23540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07soc/intel/skylake: Add Kabylake PCH H device ID'sV Sowmya
Add PCH,MCH,IGD,I2C,PMC,SMBUS,XCHI and UART IDs for PCH H. Change-Id: I52b38457bc727735ceb5003cbccda6d7ba3340a2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23382 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-05soc/intel/skylake: Set PsysPl3 and Pl4Shelley Chen
If given a value for PsysPl3 and/or Pl4, set the appropriate MSR. BUG=b:71594855 BRANCH=None TEST=boot up and check MSRs in OS to make sure values are set as expected. Test on Fizz, which will set these values in mainboard. Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-02-05soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC config spaceHannah Williams
read_resources in common/block/pmc/pmc.c is corrupting the BAR at offset 0x20. pch_pmc_read_resources | pci_dev_read_resources | pci_get_resource Within pci_get_resource, the BAR is read and written back. Since read of ACPI BAR does not return the correct value, the subsequent write corrupts the BAR. Hence re-programming the BAR. Also, reading PMC STATUSCOMMAND register does not return bit 0 correctly in pci_dev_enable_resources. This causes IO SPACE ACCESS to get disabled. Hence making sure IO ACCESS gets enabled by setting dev->command TEST=Can boot to OS Without this change coreboot will be stuck at "Disabling ACPI via APMC:" Change-Id: I27062419d06127951ecbbb641835d06ca39ff435 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23230 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26soc/intel/cannonlake: Add Cannonlake D0 support in mpinit and reportLijian Zhao
Both early platform information reporting in bootblock and common code CPU driver will add support for cannonlake D0 stepping processor. BUG=None TEST=Boot up system with D0 stepping CPU installed, check serial log that can display as D0 stepping. Change-Id: I76ee974ee027100d7853a110f95b1601987492e4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25drivers/i2c/designware: reduce API complication for bus configAaron Durbin
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement that callback for obtaining the bus config. However, we're currently forcing another parameter of struct device so one can do the lookup. This works for Intel-based systems since the struct device was needed to program the BAR, etc. However, from an API standpoint, it just complicates matters by needing to obtain the struct device. The SoC already has knowlege of its own devices so it can get the config itself by bus number. Therefore, remove that contraint from the API. BUG=b:70232394 Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23420 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25soc/intel/skylake: Clean up the skylake PCH H device ID macrosV Sowmya
Rename the device ID macros as per the skylake PCH H external design specification. Change-Id: I4e80d41380dc1973d02bc69ac32aad5c4741a976 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23381 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-24drives/i2c/designware: incorporate device_operations supportAaron Durbin
In ramstage the device_operations are needed for the i2c designware host controller. Move the intel/common/block/i2c implementation into the generic driver so other platforms can take advantage of it. BUG=b:72121803 Change-Id: Id249933fadcc016bfba00e7a6d65f56dfc220724 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-24drivers/i2c/designware: namespace soc functionsAaron Durbin
Rename the following functions to ensure it's clear that the designware i2c host controller driver is the one that these functions are associated with: i2c_get_soc_cfg() -> dw_i2c_get_soc_cfg() i2c_get_soc_early_base() -> dw_i2c_get_soc_early_base() i2c_soc_devfn_to_bus() -> dw_i2c_soc_devfn_to_bus() i2c_soc_bus_to_devfn() -> dw_i2c_soc_bus_to_devfn() BUG=b:72121803 Change-Id: Idb7633b45a0bb7cb7433ef5f6b154e28474a7b6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23371 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17soc/intel/common: Add option to pass SoC IO resourceSubrata Banik
This patch ensures common block has option to reserve IO resources based on SOC requirements. Also add pch_lpc_ prefix to maintain same function nomenclature across all intel common block. Change-Id: Ic00af688104bcea1aff06be6cbb20208a60e5f1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12soc/intel/common/block: Check for NULL before dereferenceShaunak Saha
We check for NULL from the return of function acpi_device_path before passing it to acpigen_write_scope to avoid NULL pointer dereference. Change-Id: I997461c9b639acc3c323263d304333d3a894267c Found-by: Klockworks Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/23094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12soc/intel/common: Add Intel HDA common block driverDuncan Laurie
There is common HDA code in soc/intel/common that provides generic HDA support functions, but it does not provide a driver. This change adds a common block driver for HDA that provides a ramstage driver for SOCs that need to initialize an HDA codec. This was tested on a board with an HDA codec to ensure that it properly detected it and ran the codec init steps. Change-Id: I41b4c54d3c81e1f09810cfaf934ffacafca1cf38 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-23soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2Furquan Shaikh
Even though kaby lake and cannon lake are using the same GSPI controller, bit meanings (for polarity and state) in SPI_CS_CONTROL register are significantly different. This change provides a new Kconfig option that can be selected by SoCs using these new bit definitions of SPI_CS_CONTROL. Common code takes care of setting the right value for polarity and state field depending upon the version selected by SoC. BUG=b:70628116 Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-23soc/intel/{apollolake, cannonlake, common, skylake}: Add _soc_ prefix in ↵Subrata Banik
weak function This patch ensures all soc function name is having _soc_ prefix in it. TEST=Able to compile SMM common code for all supported SOC. Change-Id: Iab1b2f51eaad87906e35dbb9e90272590974e145 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/intel: Treat time-out as failure in HECILijian Zhao
If HECI gets times out when waiting for read slots, there's no need to read back reply message to decide if the HECI recieve successed or not. Otherwise, system will stuck after global reset required. BUG=b:707290799 TEST=Boot up meowth board without battery, and confirm hard reset got trigged after heci time out. Change-Id: I7c1655284d7027294d8ff5d6a5dbbebe4cbd0c47 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22ic2/designware: Move Intel i2c logic to shared driverChris Ching
BUG=b:70232394 BRANCH=none TEST=emerge-reef coreboot emerge-glados Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/intel/common: Add missing SoC common function into SMM librarySubrata Banik
Modify SMM common code in order to accommodate SKL, CNL, APL, GLK SOC code. Change-Id: Ie9f90df3336c1278b73284815b5197400512c1d2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22869 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-21soc/intel/common: Add API to restore power failure into PMC common codeSubrata Banik
PMC config register need to program to define which state system should be after reapplied power from G3 state. 0 = System will return to S0 state 1 = System will return to S5 state 2 = System will return to previous state before failure Refer to EDS for detailed programming sequence. Change-Id: I0ce2cc77745d00a8cfe3eed7c6372af77e063d02 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22838 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-16soc/intel/common/fast_spi: implement spi_flash_ctrlr_protect_region()Aaron Durbin
In the fast spi support implement the callback for flash_protect(). This removes the need for having SOC_INTEL_COMMON_SPI_FLASH_PROTECT Kconfig option as well spi_flash_get_fpr_info() and separate spi_flash.[ch]. BUG=b:69614064 Change-Id: Iaf3b599a13a756262d3f36bae60de4f7fd00e7dc Signed-off-by: Aaron Durbn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-14soc/intel/common/block/i2c: fix orphaned Kconfig optionsAaron Durbin
The SOC_INTEL_COMMON_LPSS_I2C option is no longer used. Likewise, the SOC_INTEL_COMMON_LPSS_I2C_DEBUG option which is dependent on SOC_INTEL_COMMON_LPSS_I2C is by definition not used either. Therefore, remove SOC_INTEL_COMMON_LPSS_I2C and change the name/dependency for SOC_INTEL_COMMON_LPSS_I2C_DEBUG to SOC_INTEL_COMMON_BLOCK_I2C_DEBUG. BUG=b:70232394 Change-Id: Icd77f028b77d8f642690a50be4ac2c50d9ef511a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22874 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2017-12-13soc/intel/common/block: Add option to have subsystem_id in common pci driverSubrata Banik
This patch ensures all Intel common PCI devices can have subsystem ID programmed along with PCI resource enabling (.enable_resources) as part of PCI enumeration process. TEST=Build and boot KBL/CNL/APL/GLK to ensure PCI subsystem ID getting programmed. Example: Enabling resources... PCI: 00:00.0 subsystem <- 8086/590c PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/591e Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22768 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11soc/intel/cannonlake: Add support for D0 steppingLijian Zhao
D0 stepping with CPUID 0x60663 need to be added in coreboot. TEST=Boot up with D0 stepping processor Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07soc/intel/apollolake: add ability to enable eSPIBora Guvendik
Add config option to enable eSPI TEST=Boot to OS Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07soc/intel/common/block: Add Intel common Graphics controller supportSubrata Banik
SoC need to select specific macros to compile common graphics code. Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-02soc/intel/common/block: Add Intel common PMC controller support for KBL, APLSubrata Banik
SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-30soc/intel/common: Add Intel SRAM common code supportV Sowmya
Add SRAM code support in intel/common/block to read and use fixed resources on BAR0 and BAR2 for SRAM. Change-Id: I7870a3ca09ac7b57eb551d5eb42d8361d22f362a Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/22607 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-28soc/intel/skylake: Make use of Intel common DSP blockSubrata Banik
TEST=Build and boot soraka/eve. Change-Id: I8be2a90dc4e4c5eb196af57045d2a46b7f0c9722 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-28intel/common/block: Add SKL CSME device IDSubrata Banik
This patch ensures SKL code is using CSME common PCI driver. TEST=Build and boot soraka/eve. Change-Id: Ic229c60e434d83eb4a3e5392ce90a7d47fddbd73 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
There is currently no case where a struct cpu_device_id instance needs to be modified. Thus, declare all instances as const. Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15soc/intel/common: Use HOST_CSR to get circular Buffer DepthSubrata Banik
As per CSME BWG section 3.4.4. The Circular Buffer Depth can find by checking B0:D22:F0 MMIO_HOST_CSR register. TEST=Build and boot eve/soraka/reef/cnl-rvp Change-Id: I1d3c09077e040b5c32b3c8be867a07f392ea4e1c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15soc/intel/common: Add HECI message retry countSubrata Banik
Send/Receive HECI message with 5 retry count in order to avoid HECI message failure. TEST=Build and boot eve/soraka/reef/cnl-rvp Change-Id: I76662f8080fe312caa77c83d1660faeee0bdbe7e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22443 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15soc/intel: Enable ACPI DBG2 table generationDuncan Laurie
Enable the ACPI DBG2 table generation for Intel boards. This is a Microsoft defined ACPI extension that allows an OS to know what the debug port is on a system when it is not enabled by the firmware, so it does not show up in the coreboot tables and cannot be easily found by a payload. broadwell: Use byte access device, set up only when enabled since it relies on the port being put in byte access mode and using this serial port for debug was not standard in this generation. skylake: Enable for the configured debug port. Skylake uses intelblocks for UART but not ACPI. common: Enable for the configured debug port. This affects apollolake and cannonlake. Tested by compiling for apollolake/broadwell, tested by reading the DBG2 ACPI table on kabylake board and using IASL to dump: [000h 0000 4] Signature : "DBG2" [004h 0004 4] Table Length : 00000061 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0035 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 000F [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [036h 0054 2] OEM Data Offset : 0000 [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FE034000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 15] Namepath : "\_SB.PCI0.UAR2" Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-13soc/intel/common: Add error print in common i2cLijian Zhao
Print error message when using common i2c without default clock defined. TEST=Do not define default clock in Kconfig, compile will stop for assertion. Change-Id: I803f97698b3928e6b64df0010e71a6ded1400f87 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-11-11soc/intel/common/block: Add Intel common SPI supportSubrata Banik
SOC need to select specific macros need to compile common SPI code. Change-Id: I82f7d1852d12ca37f386b64a613a676753da959c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10soc/intel/common: Fix CSE common code to accomodate Skylake/KabylakeSubrata Banik
This patch ensures Skylake/Kabylake soc can make use of common CSE code in order to perform global reset using HECI interface. TEST=Build and boot on soraka/eve/reef/cnl-rvp Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07src: Fix all Siemens copyrightsMario Scheithauer
Some Siemens copyright entries incorrectly contain a dot at the end of the line. This is fixed with this patch. Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-04soc/intel/common: Add common dsp driverLijian Zhao
Audio DSP pci driver can be common across different platforms. TEST=N/A. Change-Id: Ia9206657864b8795799dc71af54996017c1eec57 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22232 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2017-11-03soc/intel/common/block/lpc: Make integer literal unsigned longPaul Menzel
``` CC romstage/soc/intel/common/block/*/lpc_lib.o src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the '<<' expression is undefined alignment = 1 << (log2_ceil(window_size)); ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~ ``` Change-Id: I9bf2283e23ca7739a7e5b0993d9b6034ea28fb78 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-03soc/intel/common/block: Make integer literal unsigned longPaul Menzel
Fix the warning below by making the integer literal unsigned. ``` CC bootblock/soc/intel/common/block/*/lpc_lib.o src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the \ '<<' expression is undefined alignment = 1 << (log2_ceil(window_size)); ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~ ``` Found-by: Clang static analyzer scan-build (clang version 4.0.1-6 (tags/RELEASE_401/final)) Fixes: e237f8b7 (soc/apollolake/lpc: Open I/O to LPC based on resource allocation) Change-Id: I094fb469f020f3c1fae936e304b4458858842a8e Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-03soc/intel/apollolake: Add APL CPU device IDMario Scheithauer
Add Apollo Lake CPU device ID for E0 stepping. Change-Id: I28fa222cd28b783d22c347cdbbd769e66bf10c30 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-31intel/common/smbus: increase spd read performanceKane Chen
This change increases the spd read performance by using smbus word access. BUG=b:67021853 TEST=boot to os and find 80~100 ms boot time improvement on one dimm Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-27intel/common/p2sb: Add common p2sb driverLijian Zhao
Add common p2sb device driver that will use fixed resource instead dynamic assigned by PCI enumeration. TEST=None Change-Id: Ie3f7036a5956e3db1662678aaf43023ff79ae10e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-20intel/common/block/sgx: Add API to enumerate SGX resources and update GNVSPratik Prajapati
Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 is called to enumerate SGX resources. Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19soc/intel/common/block/pmc: Add helper routines to read/write PM1_CNTFurquan Shaikh
This change adds and uses helper routines for reading and writing PM1_CNT register. BUG=b:67874513 Change-Id: I69b9347ab54a392b67ba733eb00922583dc1ee5f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22081 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-19soc/intel/common/block/pmc: Add new function pmc_fill_pm_reg_infoFurquan Shaikh
This change creates a new function pmc_fill_pm_reg_info that fills chipset_power_state structure with all the PM register information. On the other hand, already existing pmc_fill_power_state calls into pmc_fill_pm_reg_info and then checks and returns previous sleep state information. This allows caller to get all the PM register information when previous sleep state is not relevant. BUG=b:67874513 Change-Id: Idc91e4aef5379549355aceb685f7afafa6a220c5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22080 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-17soc/intel/common/block/pmc: Move pmc_disable_all_gpe to romstageFurquan Shaikh
Instead of disabling all GPEs during PMC init in bootblock, this change moves it to pmc_fill_power_state which allows romstage to correctly fill up GPE_EN registers in chipset_power_state. This is essential for correctly identifying the wake source. Disabling all GPEs was added recently in change 74145f76 (intel/common/pmc: Disable all GPEs during pmc_init) because keeping GPEs enabled in coreboot while enabling SMI could lead to side-effects as explained in the change. Moving pmc_disable_all_gpe to pmc_fill_power_state should be safe as that happens before SMI is enabled in coreboot. TEST=Verified that GPE-based wake source is correctly identified. Also, no issues observed while resuming from S3. Change-Id: I8e992ad09ffdefba62de11fa572e783715776bf1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22033 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16soc/intel/common: sanity check ebda signatureAaron Durbin
It's possible for chipsets utilizing ebda to cache the cbmem_top() value to be called prior to the object being entirely setup. As such it's important to check the signature to ensure the object has been initialized. Do that in a newly introduced function, retrieve_ebda_object(), which will zero out the object if the signature doesn't match. Change-Id: I66b07c36f46ed9112bc39b44914c860ba68677ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-16console/flashconsole: Enable support for postcarYouness Alaoui
If FSP 2.0 is used, then postcar stage is used and the flashconsole as well as spi drivers needed to be added. Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16intel/common: CAR setup CQOSNaresh G Solanki
Enable CQOS on Geminilake. In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF. Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK. Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right bits. BUG=None TEST= Build for Geminilake platform i.e., glkrvp & check for successful CAR setup. Even verified the same on APL platform i.e., on Reef Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com Reviewed-on: https://review.coreboot.org/21701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12intel/common/pmc: Disable all GPEs during pmc_initFurquan Shaikh
If GPEs are not cleared during pmc_init, it could result in issues if standard wake events are generated while coreboot is initializing. e.g. (Observed on soraka): 1. Suspend to S3 2. Lidclose 3. Lidopen 4. EC wakes up the host using WAKE# pin 5. On wakeup, pmc_init occurs which does not clear GPEs 6. MP init enables SMI 7. In order to add wake event to elog, coreboot sets wake mask on the EC, which causes the EC to assert WAKE#. 8. Since WAKE# is asserted, it results in an SMI#. However, EC does not de-assert WAKE# until host queries and clears the host event bit (which does not happen since coreboot is stuck in handling the SMIs). This is one of the issues that can occur when GPEs are unnecessarily enabled in coreboot. Before the move to PMC common library, SKL PMC driver set all GPEs to 0 and hence this issue did not occur. This change explicitly disables all GPEs during pmc init in order to avoid any side-effects. BUG=b:67712608 TEST=Verified that device resumes fine using lidclose/lidopen to suspend and resume. Change-Id: Ic5be02a23a8dbf43c4d7adf00251639ded4a94c9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21969 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12soc/intel/common: Clean up PMC library GPE handling APIFurquan Shaikh
1. Update gpe handling function names to explicitly mention if they are operating on: a. STD GPE events b. GPIO GPE events c. Both 2. Update comment block in pmclib.h to use generic names for STD and GPIO GPE registers instead of using any one platform specific names. BUG=b:67712608 Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21968 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12soc/intel/skylake: Enable bus master for sataKane Chen
The bus master needs to be enabled so that the busy bit in AHCI PORT_TFDATA will be cleared by controller when depthcharge tries to wait for sata to complete spin-up during AHCI init. Otherwise, the timeout will happen and cause 5 seconds delay in depthcharge. BUG=b:37639063 BRANCH=none TEST=verify that the sata timeout is gone in depthcharge Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/21890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-05soc/intel/common/block: Manage power state variable from common PMC blockShaunak Saha
This patch helps managing power state variables from within the library. Adds migrate_power_state which migrates the chipset power state variable, reads global power variable and adds it in cbmem for future use. This also adds get_soc_power_state_values function which returns the power state variable from cbmem or global power state variable if cbmem is not populated yet. Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21851 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/intel/{common,apollolake}: Add checks to handle negative valuesRizwan Qureshi
Fix issues reported by coverity scan in the below files. src/soc/intel/common/block/i2c 1375440: Improper use of negative value 1375441: Improper use of negative value 1375444: Improper use of negative value src/soc/intel/apollolake/i2c.c 1375442: Unsigned compared against 0 Change-Id: Ic65400c934631e3dcd3aa664c24cb451616e7f4d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/cannonlake: Fill the SMI usageLijian Zhao
Add SMM support for Cannonlake on top of common SMM, also include the SMM relocate support. Change-Id: I9aab141c528709b30804d327804c4031c59fcfff Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/common/block: Update LPC libRavi Sarawadi
Add support for following functionality: 1. Set up PCH LPC interrupt routing. 2. Set up generic IO decoder range settings. 3. Enable CLKRUN_EN for power gating LPC. Change-Id: Ib9359765f7293210044b411db49163df0418070a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02soc/intel/common/block: Move power button SMI functions to common PMC blockShaunak Saha
This patch moves the functions update_pm1_enable and read_pm1_enable to common block PMC. We rename the functions to pmc_update_pm1_enable and pmc_read_pm1_enable to keep semantics consistent. Change-Id: I9a73a6348fc22367ee2e68bf2c31823ebfefc525 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-27smbus: Fix a typo ("Set the device I'm talking too")Jonathan Neuschäfer
Change-Id: Ia14bbdfe973cec4b366879cd2ed5602b43754260 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27soc/intel/common: Add Cannonlake PCI idLijian Zhao
Add extra pci ids of CNLU and CNLY into common code. Change-Id: Ibbf3d500a780cc6a758fda1ddbec2b9953fb5a97 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-25soc/intel: lpc: Use IS_POWER_OF_2 instead of open-coding itJonathan Neuschäfer
Change-Id: I7a10a3fa5e1e9140a558f61109d0c9094d46e521 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-22soc/intel/common: Add function to get soc reserved memory sizeSubrata Banik
This patch ensures to consider soc reserved memory size while allocating DRAM based resources. Change-Id: I587a9c1ea44f2dbf67099fef03d0ff92bc44f242 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22soc/intel/common: Add intel common EBDA supportSubrata Banik
This patch provides EBDA library for soc usage. Change-Id: I8355a1dd528b111f1391e6d28a9b174edddc9ca0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22soc/intel/skylake: add Kabylake Celeron base SKUGaggery Tsai
This patch adds the support for Kabylake Celeron base SKU with PCH ID 0x9d50. BRANCH=none BUG=b:65709679 TEST=Ensure coreboot could recognize the Kabylake Celeron base SKU and boot into OS. Change-Id: I9c6f7bf643e0dbeb132fb677fcff461244101a55 Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quantatw.com> Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com>
2017-09-21soc/intel/apollolake: Make SCI configurableMario Scheithauer
The System Control Interrupt is routed per default to IRQ 9. Some mainboards use IRQ 9 for different purpose. Therefore it is necessary to make the SCI configurable on Apollo Lake. Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-20vboot: remove init_vbnv_cmos()Aaron Durbin
Instead of having each potential caller deal with the differences of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the correct logic within the callee, cmos_init(), for handling the vbnv in CMOS. The internal __cmos_init() routine returns when the CMOS area was cleared. BUG=b:63054105 Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-19soc/intel/common/block: Add pci device id for CNL-YBora Guvendik
Change-Id: I2820a39a34a80d066ca5cb364f67dbde0203803e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-16soc/intel/common: smm.h: Fix copyright yearJonathan Neuschäfer
Intel obviously didn't exist in 201 :-) Change-Id: I230d3b92ec6832fcea056fd3d099147002274d73 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-15soc/intel/skylake: Move UNCORE PRMRR base and mask defines.Pratik Prajapati
UNCORE PRMRR BASE and MASK MSRs are not common, so move to SOC specific header file and rename the #define to start with MSR_* Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15soc/intel/common/sgx: use SOC specific API to get PRMRR base and maskPratik Prajapati
Use soc_get_uncore_prmmr_base_and_mask() API to get PRMRR base and mask. Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21246 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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