coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-03-28	soc/intel/common: Move support to log XHCI wake events	Karthikeyan Ramasubramanian
	The policy to identify and log the XHCI wake events is similar between skylake and apollolake. Hence move the similar parts to a common location. BUG=b:123429132 BRANCH=None TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up events due to USB are logged into the event logs. 6 \| 2019-03-21 09:22:18 \| S0ix Enter 7 \| 2019-03-21 09:22:22 \| S0ix Exit 8 \| 2019-03-21 09:22:22 \| Wake Source \| PME - XHCI (USB 2.0 port) \| 9 9 \| 2019-03-21 09:22:22 \| Wake Source \| GPE # \| 13 10 \| 2019-03-21 09:23:20 \| ACPI Enter \| S3 11 \| 2019-03-21 09:23:30 \| Wake Source \| PME - XHCI (USB 2.0 port) \| 9 12 \| 2019-03-21 09:23:30 \| ACPI Wake \| S3 13 \| 2019-03-21 09:23:30 \| Wake Source \| GPE # \| 13 Change-Id: Ia6643342e3292984e422ff3c3fcd4bc0d99f947e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-06	soc/intel/common/block: Add Intel XHCI driver support	Subrata Banik
	Create sample model for common Intel XHCI driver. Change-Id: I81f57bc713900c96d998bae924fc4d38a9024fe3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18221 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>