coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-10-30	soc/intel/common/block/usb4: Add TCSS XHCI driver for SSDT generation	Duncan Laurie
	In order to generate ACPI entries for USB devices attached to the USB4/TBT/TCSS/North XHCI device it needs to have a driver that will enumerate static devices on the bus. This driver does that and nothing else. BUG=b:151731851 TEST=boot on volteer and check for USB devices on \_SB.PCI0.TXHC.RHUB Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I5a2ff1cd1bed557e793d45119232cf87032ddd7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46851 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14	soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports	Duncan Laurie
	This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL. It assigns the USB4 port number and marks the port as external and hotplug capable. Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44915 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14	soc/intel/common: Add PCI driver for USB4 ports	Tim Wawrzynczak
	In order to enable SSDT generation for the DMA component of Intel USB4 ports, a PCI driver is required. This patch more or less adds a `scan_bus` callback that will handle non-PCI devices downstream. Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>