coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-12-10	soc/intel/common: Add Jasperlake Device IDs	rkanabar
2019-09-29	soc/intel: Rename <intelblocks/chip.h>	Kyösti Mälkki
2019-08-28	soc/intel/common/block: Provide mmc.c for setting dll registers	Kane Chen
2019-05-29	Clean up unused arch/early_variables.h header	Arthur Heymans
2019-05-23	intel/common/block/scs: Add ability to send early CMD0, CMD1	Bora Guvendik
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-02-26	soc/intel/common: Include cometlake PCH IDs	Ronak Kanabar
2019-01-23	soc/{amd,intel}: Remove needless '&' on function pointers	Elyes HAOUAS
2018-11-07	soc/intel/common: Include Icelake device IDs	Aamir Bohra
2018-10-17	soc/intel/cannonlake: Add new cannon lake PCH-H support	praveen hodagatta pranesh
2018-06-04	src/soc: Get rid of whitespace before tab	Elyes HAOUAS
2017-12-13	soc/intel/common/block: Add option to have subsystem_id in common pci driver	Subrata Banik
2017-08-04	soc/intel/common: Add Cannonlake pci ids for common	Lijian Zhao
2017-06-16	soc/intel/common/block: Add Intel common SCS code support	Bora Guvendik