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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ic5a920bfe1059534566ceab85a97219dd56f069e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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'else' is not needed after a 'break' or 'return'.
Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33336
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is spotted using "./util/lint/kconfig_lint"
While at it, do the check in C and not the preprocessor.
Change-Id: Icfda267936a23d9d14832116d67571f42f685906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use of device_t is deprecated.
Change-Id: Ic29891d78514db3b7eed48414a14e4ff579436c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30004
Reviewed-by: David Guckian
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch to fix KW issue due to msg, data and response pointers NULL
check fail.
Change-Id: I39324514079f240ba1683a04e579de85485299bf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The intelblock code is common code already used by appololake and
cannonlake platform. The denverton platform also use a similar gpio
controller so the intelblock code can be used as well.
Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24928
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This function performs SBI communication
Input:
* PID: Port ID of the SBI message
* Offset: Register offset of the SBI message
* Opcode: Opcode
* Posted: Posted message
* Fast_Byte_Enable: First Byte Enable
* BAR: base address
* FID: Function ID
* Data: Read/Write Data
* Response: Response
Output:
* 0: SBI message is successfully completed
* -1: SBI message failure
Change-Id: I4e49311564e20cedbfabaaceaf5f72c480e5ea26
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23809
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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PCR_BASE_ADRESS may be zero if SOC Kconfig didn't define the non zero
default value.
TEST=Remove the PCR_BASE_ADDRESS config in Apollolake Kconfig file and
build.
BUG=None
Change-Id: I396aa1a3e89507c90e17229a986de5d2c0887c9c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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IOSF_SB message space is used to access registers mapped
on IOSF-SB. These registers include uncore CRs (configuration
registers) and chipset specific registers. The Private
Configuration Register (PCR) space is accessed on IOSF-SB
using destination ID also known as Port ID.
Access to IOSF-SB by the Host or System Agent is possible
over PSF via the Primary to Sideband Bridge (P2SB). P2SB will
forward properly formatted register access requests as CRRd and
CRWr request via IOSF-SB.
Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18669
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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