aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/common/block/lpc
AgeCommit message (Collapse)Author
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-16intel/common/block/lpc: Add new device IDs for Lewisburg PCHBryantOu
Add C621A, C627A and C629A SKU IDs. C621A is used in the Whitley Product. We need to add device ID for setting LPC resources. Refer to Intel C620 series PCH EDS (547817). Change-Id: I19a4024808d5aa72a9e7bd434613b5e7c9284db8 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40395 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-18soc/intel/skylake: Control fixed IO decode from devicetreeWim Vervoorn
The current implementation doesn't allow custom values for the LPC IO decodes and IO enables. Add the lpc_ioe and lpc_iod values. If they are not zero, they will be used instead of the current handling for COMA and COMB. BUG=N/A TEST=tested on facebook monolith Change-Id: Iad7bb0e44739e8d656a542c79af7f98a4e9bde69 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38748 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25soc/intel/common: Update Jasper Lake Device IDsMeera Ravindranath
Update Jasper Lake CPU, SA and PCH IDs. BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-19soc/intel/common/block/lpc: Drop unnecessary helper functionSubrata Banik
This patch removes unnecessary helper function pch_lpc_interrupt_init() and directly uses soc_pch_pirq_init() function to avoid redundant device NULL check. TEST=Able to build and boot CML platform. Change-Id: I3d11afb7e98f9b7f84beb2fdf308bbffeb3bbff7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38952 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11soc/intel/common/block/lpc: Add lpc_get_fixed_io_decodeWim Vervoorn
Add function to return the fixed io decode ranges contained in register 0x80 of the LPC interface. BUG=N/A TEST=build Change-Id: Ie46d7c9d7a399a8489c030d906f75ba61db19cc4 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38745 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30soc/intel/common/block/lpc: Add CMP-H LPC IDsGaggery Tsai
This patch adds CMP-H LPC IDs. TEST=Build an image and boot with discrete TPM chip. Enable measured boot and kernel could get the measured data from TPM chip. Change-Id: I7eac8b0514f79b47a05973210e2472dd1dc3d0ed Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38251 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22soc/intel/common: Add Elkhartlake Device IDsTan, Lean Sheng
Add Elkhartlake CPU, SA and PCH IDs. EHL PCH is code named as MCC. Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-12soc/intel: Fix ACPI device operations initializationKarthikeyan Ramasubramanian
Initialize ACPI device operations only when CONFIG_HAVE_ACPI_TABLES is enabled. BUG=None TEST=Build Test Change-Id: I5c5266885d8b08338d17a87bb95110765882120e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-10soc/intel/common: Add Jasperlake Device IDsrkanabar
Add Jasperlake SA and PCH IDs Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-11-14soc/intel/tigerlake: Include few more Tigerlake device IDsSubrata Banik
This patch performs below operations 1. Add few more MCH, ESPI and IGD IDs 2. Remove TGL-H IDs 3. Rename existing as per applicable names 4. Remove TODO from report_platform.c file 5. Include TGL IDs into report_platform.c file Change-Id: I7bb3334d0fe8ba72e394d1a63b3a73840b4eaf2f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-11-05soc/intel/common: Include Tigerlake device IDsRavi Sarawadi
Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs. BUG=None BRANCH=None TEST=Build 'emerge-tglrvp coreboot' Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I19047354718bdf510dffee4659d885f1313a751b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-10-18soc/intel/common: lpc/espi: fix wrong lock bitMichael Niewöhner
This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance with doc#332691-003EN and doc#334819-001. Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-08device: Use scan_static_bus() over scan_lpc_bus()Nico Huber
Devices behind LPC can expose more buses (e.g. I2C on a super-i/o). So we should scan buses on LPC devices, too. Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06soc/intel/skylake: Add Lewisburg family PCH supportMaxim Polyakov
This patch adds Lewisburg C62x Series PCH support by adding the Production and Super SKUs of the following PCI devices: - LPC or eSPI Controllers, - PCI Express Root Ports, - SSATA and SATA Controllers, - SMBus, - SPI Controller, - ME/HECI, - Audio, - P2SB, - Power Management Controller. These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-07-31soc/intel/skl: Add C232 chipset and reorder IDsFelix Singer
This patch ... - adds the PCH ID for C232 chipset, - renames "Premium" chipset to "HM170" (because of same IDs), - reorders the Skylake-H PCH IDs ascending by hex values. Used documents: - Intel 332690-005EN Change-Id: I859975fe7bcd3c10dead8fe150a2fbead9c64a51 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-30soc/intel/cannonlake: Add new PCI IDsFelix Singer
* PCH IDs: H310, H370, Z390, B360, C242, HM370 * IGD IDs: Another variant of UHD-Graphics 630 * MCH/CPU IDs: Used at i3-8100 Used documents: * 337347-005 TESTED=Gigabyte Z390M Gaming Change-Id: I5be88ef23359c6429b18f17bcffbffb7f10ba028 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34600 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18soc/intel: Use config_of()Kyösti Mälkki
Change-Id: I0727a6b327410197cf32f598d1312737744386b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
2019-07-17soc/intel/cannonlake: Add device Ids for new CFL SKUs supportLean Sheng Tan
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs - Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246 - Make some minor alignments & naming corrections to align with the rest TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-12soc/intel/common: Add CM246 LPC device idNico Huber
Change-Id: Ic57ccf48988afbbba256172a7540bb02b88d1bbd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34163 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11soc/intel/common: Check bios_size and window_size after MIN operationJohn Zhao
Clang Static Analyzer version 8.0.0 detects that the result of log2_ceil(bios_size) and log2_ceil(window_size) is undefined if the value of bios_size and window_size are negative. Add negative value Check for bios_size and window_size after MIN operation. Change-Id: I28577b6e0ba0ab45bb7804c17ba1f26c4b078b15 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-24Replace ENV_RAMSTAGE with ENV_PAYLOAD_LOADERSubrata Banik
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set to ENV_RAMSTAGE. This approach will help to add future optimization (rampayload) in coreboot flow if required. Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-06-13soc/intel/icelake: Replace PCI device LPC to ESPI as per EDSSubrata Banik
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same. This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block. Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2019-06-08src/soc/intel/skylake/bootblock: Add SPT C236 to PCH TableChristian Walter
Add Skylake C236 to the PCH Table. The one which was already in there is actually the CM236 and not the C236. This can be checked in datasheet: 100-series-chipset-datasheet-vol-1 p. 25. Change-Id: I435927f15e9d3219886375426b09c68632dfe3d9 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-29soc/intel/common: Check bios_size and window_size after MIN operationJohn Zhao
Clang Static Analyzer version 8.0.0 detects that log2_ceil(bios_size) and log2_ceil(window_size) are garbage or undefined if the value of bios_size and window_size is zero. Check bios_size and window_size after MIN operation to prevent error. TEST=Built and boot up to kernel. Change-Id: Ifc3f3da52d129ef5d6063a46b045603a236be759 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-28src/include/device/pci_ids.h: Add Kabylake C236 DeviceChristian Walter
Change-Id: Ib11981543575311a32896df385d44cf30aa9387f Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32964 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06soc/skylake: Add missing PCH IDsMarius Genheimer
Added IDs for: - H170 - Z170 - Q170 - Q150 - B150 Used documents: - 332690-005EN Tested on Gigabyte GA-Z170N-WIFI Change-Id: If20a2b764afa02785a97948893dbc5b5f60aff60 Signed-off-by: Marius Genheimer <mail@f0wl.cc> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32517 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-06soc/intel/skylake: Add H110 PCH seriesMaxim Polyakov
This patch adds support H110 chipset (Sunrise Point) for Skylake and Kaby Lake processor families by adding the corresponding IDs. It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU). Change-Id: I85ba65ac860687b0f9fd781938e5cac21a1b668d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31602 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-26soc/intel/common: Include cometlake PCH IDsRonak Kanabar
Add cometlake specific PCH IDs Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03soc/intel: Fix bad uses of __SIMPLE_DEVICE__Kyösti Mälkki
Cases of *dev = PCI_DEV(b,d,f) are invalid. Not caught because files only build with __SIMPLE_DEVICE__ defined. Remove cases of testing __SIMPLE_DEVICE__ in files that are not build for ramstage. Change-Id: If10a0efa187c9b1d9a5577008aa46f050f0aa309 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-05soc/intel/common/lpc_lib: Add function to disable LPC Clock RunNico Huber
Needed to fix up FSP-S bug on Apollo Lake. Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-08soc/intel/skylake: Add PCH sku id's supported for KBLPraveen hodagatta pranesh
This patch also add new SKL PCH-H device id's in soc platform reporting and common lpc driver. BUG=None TEST=Booted kabylake RVP11 with HM175 SKL PCH-H and verified the device id in serial logs. Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-07soc/intel/common: Include Icelake device IDsAamir Bohra
Add Icelake specific CPU, System Agent, PCH, IGD device IDs. Change-Id: I2c398957ffbc9bb0e5b363740d99433075ca66a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake RVP8 platforms. - Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB, SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device. - Add new device IDs to intel common code respectively. - Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8. - CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c is modified accordingly. - Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8. BUG=None TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices are enumerated and cross checked devices ids in serial logs and UEFI shell. Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28718 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-18soc/intel/common/block: Don't use device_t in ramstageElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28631 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-20soc/intel/common: Adjust LPC Generic IO setupLijian Zhao
Check same IO ranges get programmed first, if so just skip it to avoid double programming. BUG=b:77944335 TEST=Boot up with mewoth board, and check serial log, there's no error message about "LPC: Cannot Open IO Window: ". Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25667 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-26soc/intel: Add KBL-S MCH and some KBL PCH supportGaggery Tsai
This patch adds the support for KBL-S MCH and Z270, H270, B250 and Q250 PCH chips. BUG=None BRANCH=None TEST=Boot with KBL-S CPU and B250/H270 PCHs. Change-Id: If03abb215f225d648505e05274e2f08ff02cebdc Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/25305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-03-09soc/intel/common: Enable decoding of the COMB range to LPC based on KconfigSubrata Banik
By default all Intel platform has enable IO decode range for COMA if CONFIG_DRIVERS_UART_8250IO is selected. With this patch, COMB will get enable based on CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE Kconfig selection. Also make lpc_enable_fixed_io_ranges() function returns Enabled I/O bits to avoid an additional pci configuration read to get the same data. Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-02-07soc/intel/skylake: Add Kabylake PCH H device ID'sV Sowmya
Add PCH,MCH,IGD,I2C,PMC,SMBUS,XCHI and UART IDs for PCH H. Change-Id: I52b38457bc727735ceb5003cbccda6d7ba3340a2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23382 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25soc/intel/skylake: Clean up the skylake PCH H device ID macrosV Sowmya
Rename the device ID macros as per the skylake PCH H external design specification. Change-Id: I4e80d41380dc1973d02bc69ac32aad5c4741a976 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23381 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17soc/intel/common: Add option to pass SoC IO resourceSubrata Banik
This patch ensures common block has option to reserve IO resources based on SOC requirements. Also add pch_lpc_ prefix to maintain same function nomenclature across all intel common block. Change-Id: Ic00af688104bcea1aff06be6cbb20208a60e5f1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-13soc/intel/common/block: Add option to have subsystem_id in common pci driverSubrata Banik
This patch ensures all Intel common PCI devices can have subsystem ID programmed along with PCI resource enabling (.enable_resources) as part of PCI enumeration process. TEST=Build and boot KBL/CNL/APL/GLK to ensure PCI subsystem ID getting programmed. Example: Enabling resources... PCI: 00:00.0 subsystem <- 8086/590c PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/591e Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22768 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07soc/intel/apollolake: add ability to enable eSPIBora Guvendik
Add config option to enable eSPI TEST=Boot to OS Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-11-03soc/intel/common/block/lpc: Make integer literal unsigned longPaul Menzel
``` CC romstage/soc/intel/common/block/*/lpc_lib.o src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the '<<' expression is undefined alignment = 1 << (log2_ceil(window_size)); ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~ ``` Change-Id: I9bf2283e23ca7739a7e5b0993d9b6034ea28fb78 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-03soc/intel/common/block: Update LPC libRavi Sarawadi
Add support for following functionality: 1. Set up PCH LPC interrupt routing. 2. Set up generic IO decoder range settings. 3. Enable CLKRUN_EN for power gating LPC. Change-Id: Ib9359765f7293210044b411db49163df0418070a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27soc/intel/common: Add Cannonlake PCI idLijian Zhao
Add extra pci ids of CNLU and CNLY into common code. Change-Id: Ibbf3d500a780cc6a758fda1ddbec2b9953fb5a97 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-25soc/intel: lpc: Use IS_POWER_OF_2 instead of open-coding itJonathan Neuschäfer
Change-Id: I7a10a3fa5e1e9140a558f61109d0c9094d46e521 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-22soc/intel/skylake: add Kabylake Celeron base SKUGaggery Tsai
This patch adds the support for Kabylake Celeron base SKU with PCH ID 0x9d50. BRANCH=none BUG=b:65709679 TEST=Ensure coreboot could recognize the Kabylake Celeron base SKU and boot into OS. Change-Id: I9c6f7bf643e0dbeb132fb677fcff461244101a55 Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quantatw.com> Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com>
2017-09-19soc/intel/common/block: Add pci device id for CNL-YBora Guvendik
Change-Id: I2820a39a34a80d066ca5cb364f67dbde0203803e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08soc/intel/common/block: Common ACPIShaunak Saha
This patch adds the common acpi code.ACPI code is very similar accross different intel chipsets.This patch is an effort to move those code in common place so that it can be shared accross different intel platforms instead of duplicating for each platform. We are removing the common acpi files in src/soc/intel/common. This removes the acpi.c file which was previously in src/soc/common/acpi. The config for common acpi is SOC_INTEL_COMMON_BLOCK_ACPI which can be defined in SOC's Kconfig file in order to use the common ACPI code. This patch also includes the changes in APL platform to use the common ACPI block. TEST= Tested the patch as below: 1.Builds and system boots up with the patch. 2.Check all the ACPI tables are present in /sys/firmware/acpi/tables 3.Check SCI's are properly working as we are modifying the function to override madt. 4.Extract acpi tables like DSDT,APIC, FACP, FACS and decompile the by iasl and compare with good known tables. 5.Execute the extracted tables in aciexec to check acpi methods are working properly. Change-Id: Ib6eb6fd5366e6e28fd81bc22d050b0efa05a2e5d Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-08-15soc/intel/common/block: Add LPC Common code and use it for APLRavi Sarawadi
Add LPC common code to be shared across Intel platforms. Also add LPC library functions to be shared across platforms. Use common LPC code for Apollo Lake soc. Update existing Apollolake mainboard variants {google,intel,siemens} to use new common LPC header file. Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 19:08:27 +0000