coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-04-06	soc/intel/common: Use SPDX for GPL-2.0-only files	Angel Pons
	Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic5a920bfe1059534566ceab85a97219dd56f069e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18	soc: Remove copyright notices	Patrick Georgi
	They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-09-06	soc/intel/common: Add function to set BILD bit in RTC	Rizwan Qureshi
	Add a function to set the Bios Interface Lock Down bit (bit 31) in RTC Configuration register (0x3400). This bit when set prevents the top swap enable bit (bit 0) in the RTC BUC register (0x3414) from being changed. Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30	soc/intel/common: Add support to configure top swap feature	Aamir Bohra
	RTC BUC control register provides a software interface to configure the top swap feature. This patch adds implementation to enable/disable top swap feature and gets it accessible in romstage as well. The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP is selected. To use the topswap feature a second bootblock has to be added to the cbfs. Below configs aid in doing that, INTEL_HAS_TOP_SWAP INTEL_ADD_TOP_SWAP_BOOTBLOCK INTEL_TOP_SWAP_BOOTBLOCK_SIZE Enabling and Disabling topswap, using the added API enables user to boot alternatively from either bootblock. Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/25805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-11	soc/intel/common/block: Update common rtc code	Lijian Zhao
	Move rtc init code into common area and update the implementation for apollolake to avoid build break. Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10	soc/intel/common/block: Add Intel common RTC code support	Barnali Sarkar
	Create Intel Common RTC code. This code currently only contains the code for configuring RTC required in Bootblock phase which has the following programming - * Enable upper 128 bytes of CMOS. Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18558 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins)