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Add a function to set the Bios Interface Lock Down bit (bit 31)
in RTC Configuration register (0x3400). This bit when set prevents
the top swap enable bit (bit 0) in the RTC BUC register (0x3414)
from being changed.
Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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RTC BUC control register provides a software interface to
configure the top swap feature. This patch adds implementation
to enable/disable top swap feature and gets it accessible in
romstage as well.
The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP
is selected.
To use the topswap feature a second bootblock has to be added
to the cbfs. Below configs aid in doing that,
INTEL_HAS_TOP_SWAP
INTEL_ADD_TOP_SWAP_BOOTBLOCK
INTEL_TOP_SWAP_BOOTBLOCK_SIZE
Enabling and Disabling topswap, using the added API enables user
to boot alternatively from either bootblock.
Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/25805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move rtc init code into common area and update the implementation for
apollolake to avoid build break.
Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create Intel Common RTC code. This code currently only
contains the code for configuring RTC required in Bootblock phase
which has the following programming -
* Enable upper 128 bytes of CMOS.
Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
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