coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-08-05	soc/intel/common/lpss: Add function to check for a LPSS controller	Aamir Bohra
	Add an API to check if device is a LPSS controller. This API can be used for IRQ assignments for LPSS PCI controllers, since the LPSS controllers have a requirement of unique IRQ assignments and do not share same IRQ# with other LPSS controllers. SOC code is reponsible to provide list of the LPSS controllers supported and needs to implement soc_lpss_controllers_list API, in case it needs to use this common implementation. Change-Id: I3f5bb268fc581280bb1b87b6b175a0299a24a44a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34137 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16	soc/intel/common/block/lpss: Add provision to set controller power state	Aamir Bohra
	Add function to set the power state of a LPSS controller. The API implemented can be used to enforce controllers in active state(D0) during initialization. BUG=b:135941367 Change-Id: I7540924885350de64caff91d920d6cc234154616 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34272 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03	soc/intel/common/lpss: Drop now unused lpss_clk_read()	Nico Huber
	Change-Id: I7def72e820ee1a4fa47c34b26dab9e0886ba74e6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2018-04-10	soc/intel/common: prepare for lpss clock split	Aaron Durbin
	Apparently Intel had decided to use different clock speeds for some of its IP blocks in some of its designs. The i2c designware driver has already been moved into common code allowing for its own Kconfig value. That currently leaves SPI (UART isn't using the clock currently). Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock speeds present in the system for the various IP blocks. BUG=b:75306520 Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25608 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-14	common/block/lpss: Add CLK read function into LPSS common	Subrata Banik
	This patch add new API to read LPSS CLK register. Also combine multiple LPSS_CLOCK_CTL_REG writes into a single write inside lpss_clk_update function. Change-Id: I420919ad9154c4cf426bc232c5eb59d95fd698d2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-10	soc/intel/common/lpss: Add lpss_is_controller_in_reset	Furquan Shaikh
	Add new API function lpss_is_controller_in_reset that returns whether the LPSS controller is in reset. Also, add lpss.c to smm stage so that lpss_is_controller_in_reset can be used in smihandler. BUG=b:64030366 Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10	soc/intel/common/block: Add LPSS function library	Aamir Bohra
	LPSS function library implements common register programming under lpss. Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>